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Date:      Wed, 15 Jul 2015 09:15:03 +0000
From:      "wma_semihalf.com (Wojciech Macek)" <phabric-noreply@FreeBSD.org>
To:        freebsd-arm@freebsd.org
Subject:   [Differential] [Updated, 36 lines] D3093: ARMv8 locore.S cleanup and TCR register update
Message-ID:  <9f87ed71ec84b4a79f9c3137dbc0ea95@localhost.localdomain>
In-Reply-To: <differential-rev-PHID-DREV-qvctvfcls3krqccl2a3p-req@FreeBSD.org>
References:  <differential-rev-PHID-DREV-qvctvfcls3krqccl2a3p-req@FreeBSD.org>

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wma_semihalf.com updated the summary for this revision.
wma_semihalf.com updated this revision to Diff 6962.
wma_semihalf.com added a comment.

Agreed.


REPOSITORY
  rS FreeBSD src repository

CHANGES SINCE LAST UPDATE
  https://reviews.freebsd.org/D3093?vs=6958&id=6962

REVISION DETAIL
  https://reviews.freebsd.org/D3093

AFFECTED FILES
  sys/arm64/arm64/locore.S
  sys/arm64/include/armreg.h

CHANGE DETAILS
  diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
  --- a/sys/arm64/include/armreg.h
  +++ b/sys/arm64/include/armreg.h
  @@ -200,6 +200,28 @@
   #define	TCR_TG1_4K	(2 << TCR_TG1_SHIFT)
   #define	TCR_TG1_64K	(3 << TCR_TG1_SHIFT)
   
  +#define	TCR_SH1_SHIFT	28
  +#define	TCR_SH1_IS	(0x3UL << TCR_SH1_SHIFT)
  +#define	TCR_ORGN1_SHIFT	26
  +#define	TCR_ORGN1_WBWA	(0x1UL << TCR_ORGN1_SHIFT)
  +#define	TCR_IRGN1_SHIFT	24
  +#define	TCR_IRGN1_WBWA	(0x1UL << TCR_IRGN1_SHIFT)
  +#define	TCR_SH0_SHIFT	12
  +#define	TCR_SH0_IS	(0x3UL << TCR_SH0_SHIFT)
  +#define	TCR_ORGN0_SHIFT	10
  +#define	TCR_ORGN0_WBWA	(0x1UL << TCR_ORGN0_SHIFT)
  +#define	TCR_IRGN0_SHIFT	8
  +#define	TCR_IRGN0_WBWA	(0x1UL << TCR_IRGN0_SHIFT)
  +
  +#define	TCR_CACHE_ATTRS	((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
  +				(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
  +
  +#ifdef SMP
  +#define	TCR_SMP_ATTRS	(TCR_SH0_IS | TCR_SH1_IS)
  +#else
  +#define	TCR_SMP_ATTRS	0
  +#endif
  +
   #define	TCR_T1SZ_SHIFT	16
   #define	TCR_T0SZ_SHIFT	0
   #define	TCR_TxSZ(x)	(((x) << TCR_T1SZ_SHIFT) | ((x) << TCR_T0SZ_SHIFT))
  diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
  --- a/sys/arm64/arm64/locore.S
  +++ b/sys/arm64/arm64/locore.S
  @@ -27,6 +27,8 @@
    */
   
   #include "assym.s"
  +#include "opt_kstack_pages.h"
  +
   #include <sys/syscall.h>
   #include <machine/asm.h>
   #include <machine/armreg.h>
  @@ -43,6 +45,12 @@
   #define	NORMAL_UNCACHED	1
   #define	NORMAL_MEM	2
   
  +#ifdef SMP
  +#define	SHAREABILITY	ATTR_SH(ATTR_SH_IS)
  +#else
  +#define	SHAREABILITY	0
  +#endif
  +
   /*
    * We assume:
    *  MMU      on with an identity map, or off
  @@ -180,8 +188,7 @@
   mp_virtdone:
   	ldr	x4, =secondary_stacks
   	mov	x5, #(PAGE_SIZE * KSTACK_PAGES)
  -	sub	x1, x0, #1
  -	mul	x5, x1, x5
  +	mul	x5, x0, x5
   	add	sp, x4, x5
   
   	b	init_secondary
  @@ -535,7 +542,8 @@
   		/* Device            Normal, no cache     Normal, write-back */
   	.quad	MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2)
   tcr:
  -	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K)
  +	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \
  +	    TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
   sctlr_set:
   	/* Bits to set */
   	.quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \

EMAIL PREFERENCES
  https://reviews.freebsd.org/settings/panel/emailpreferences/

To: wma_semihalf.com, zbb, emaste, andrew
Cc: imp, andrew, freebsd-arm-list, emaste

--b1_9f87ed71ec84b4a79f9c3137dbc0ea95
Content-Type: text/x-patch; charset=utf-8; name="D3093.6962.patch"
Content-Transfer-Encoding: base64
Content-Disposition: attachment; filename="D3093.6962.patch"

ZGlmZiAtLWdpdCBhL3N5cy9hcm02NC9pbmNsdWRlL2FybXJlZy5oIGIvc3lzL2FybTY0L2luY2x1
ZGUvYXJtcmVnLmgKLS0tIGEvc3lzL2FybTY0L2luY2x1ZGUvYXJtcmVnLmgKKysrIGIvc3lzL2Fy
bTY0L2luY2x1ZGUvYXJtcmVnLmgKQEAgLTIwMCw2ICsyMDAsMjggQEAKICNkZWZpbmUJVENSX1RH
MV80SwkoMiA8PCBUQ1JfVEcxX1NISUZUKQogI2RlZmluZQlUQ1JfVEcxXzY0SwkoMyA8PCBUQ1Jf
VEcxX1NISUZUKQogCisjZGVmaW5lCVRDUl9TSDFfU0hJRlQJMjgKKyNkZWZpbmUJVENSX1NIMV9J
UwkoMHgzVUwgPDwgVENSX1NIMV9TSElGVCkKKyNkZWZpbmUJVENSX09SR04xX1NISUZUCTI2Cisj
ZGVmaW5lCVRDUl9PUkdOMV9XQldBCSgweDFVTCA8PCBUQ1JfT1JHTjFfU0hJRlQpCisjZGVmaW5l
CVRDUl9JUkdOMV9TSElGVAkyNAorI2RlZmluZQlUQ1JfSVJHTjFfV0JXQQkoMHgxVUwgPDwgVENS
X0lSR04xX1NISUZUKQorI2RlZmluZQlUQ1JfU0gwX1NISUZUCTEyCisjZGVmaW5lCVRDUl9TSDBf
SVMJKDB4M1VMIDw8IFRDUl9TSDBfU0hJRlQpCisjZGVmaW5lCVRDUl9PUkdOMF9TSElGVAkxMAor
I2RlZmluZQlUQ1JfT1JHTjBfV0JXQQkoMHgxVUwgPDwgVENSX09SR04wX1NISUZUKQorI2RlZmlu
ZQlUQ1JfSVJHTjBfU0hJRlQJOAorI2RlZmluZQlUQ1JfSVJHTjBfV0JXQQkoMHgxVUwgPDwgVENS
X0lSR04wX1NISUZUKQorCisjZGVmaW5lCVRDUl9DQUNIRV9BVFRSUwkoKFRDUl9JUkdOMF9XQldB
IHwgVENSX0lSR04xX1dCV0EpIHxcCisJCQkJKFRDUl9PUkdOMF9XQldBIHwgVENSX09SR04xX1dC
V0EpKQorCisjaWZkZWYgU01QCisjZGVmaW5lCVRDUl9TTVBfQVRUUlMJKFRDUl9TSDBfSVMgfCBU
Q1JfU0gxX0lTKQorI2Vsc2UKKyNkZWZpbmUJVENSX1NNUF9BVFRSUwkwCisjZW5kaWYKKwogI2Rl
ZmluZQlUQ1JfVDFTWl9TSElGVAkxNgogI2RlZmluZQlUQ1JfVDBTWl9TSElGVAkwCiAjZGVmaW5l
CVRDUl9UeFNaKHgpCSgoKHgpIDw8IFRDUl9UMVNaX1NISUZUKSB8ICgoeCkgPDwgVENSX1QwU1pf
U0hJRlQpKQpkaWZmIC0tZ2l0IGEvc3lzL2FybTY0L2FybTY0L2xvY29yZS5TIGIvc3lzL2FybTY0
L2FybTY0L2xvY29yZS5TCi0tLSBhL3N5cy9hcm02NC9hcm02NC9sb2NvcmUuUworKysgYi9zeXMv
YXJtNjQvYXJtNjQvbG9jb3JlLlMKQEAgLTI3LDYgKzI3LDggQEAKICAqLwogCiAjaW5jbHVkZSAi
YXNzeW0ucyIKKyNpbmNsdWRlICJvcHRfa3N0YWNrX3BhZ2VzLmgiCisKICNpbmNsdWRlIDxzeXMv
c3lzY2FsbC5oPgogI2luY2x1ZGUgPG1hY2hpbmUvYXNtLmg+CiAjaW5jbHVkZSA8bWFjaGluZS9h
cm1yZWcuaD4KQEAgLTQzLDYgKzQ1LDEyIEBACiAjZGVmaW5lCU5PUk1BTF9VTkNBQ0hFRAkxCiAj
ZGVmaW5lCU5PUk1BTF9NRU0JMgogCisjaWZkZWYgU01QCisjZGVmaW5lCVNIQVJFQUJJTElUWQlB
VFRSX1NIKEFUVFJfU0hfSVMpCisjZWxzZQorI2RlZmluZQlTSEFSRUFCSUxJVFkJMAorI2VuZGlm
CisKIC8qCiAgKiBXZSBhc3N1bWU6CiAgKiAgTU1VICAgICAgb24gd2l0aCBhbiBpZGVudGl0eSBt
YXAsIG9yIG9mZgpAQCAtMTgwLDggKzE4OCw3IEBACiBtcF92aXJ0ZG9uZToKIAlsZHIJeDQsID1z
ZWNvbmRhcnlfc3RhY2tzCiAJbW92CXg1LCAjKFBBR0VfU0laRSAqIEtTVEFDS19QQUdFUykKLQlz
dWIJeDEsIHgwLCAjMQotCW11bAl4NSwgeDEsIHg1CisJbXVsCXg1LCB4MCwgeDUKIAlhZGQJc3As
IHg0LCB4NQogCiAJYglpbml0X3NlY29uZGFyeQpAQCAtNTM1LDcgKzU0Miw4IEBACiAJCS8qIERl
dmljZSAgICAgICAgICAgIE5vcm1hbCwgbm8gY2FjaGUgICAgIE5vcm1hbCwgd3JpdGUtYmFjayAq
LwogCS5xdWFkCU1BSVJfQVRUUigweDAwLCAwKSB8IE1BSVJfQVRUUigweDQ0LCAxKSB8IE1BSVJf
QVRUUigweGZmLCAyKQogdGNyOgotCS5xdWFkIChUQ1JfVHhTWig2NCAtIFZJUlRfQklUUykgfCBU
Q1JfQVNJRF8xNiB8IFRDUl9URzFfNEspCisJLnF1YWQgKFRDUl9UeFNaKDY0IC0gVklSVF9CSVRT
KSB8IFRDUl9BU0lEXzE2IHwgVENSX1RHMV80SyB8IFwKKwkgICAgVENSX0NBQ0hFX0FUVFJTIHwg
VENSX1NNUF9BVFRSUykKIHNjdGxyX3NldDoKIAkvKiBCaXRzIHRvIHNldCAqLwogCS5xdWFkIChT
Q1RMUl9VQ0kgfCBTQ1RMUl9uVFdFIHwgU0NUTFJfblRXSSB8IFNDVExSX1VDVCB8IFNDVExSX0Ra
RSB8IFwKCg==


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