Skip site navigation (1)Skip section navigation (2)
Date:      Tue, 10 May 2005 05:38:35 GMT
From:      Marcel Moolenaar <marcel@FreeBSD.org>
To:        Perforce Change Reviews <perforce@freebsd.org>
Subject:   PERFORCE change 76770 for review
Message-ID:  <200505100538.j4A5cZdX040914@repoman.freebsd.org>

next in thread | raw e-mail | index | archive | help
http://perforce.freebsd.org/chv.cgi?CH=76770

Change 76770 by marcel@marcel_nfs on 2005/05/10 05:37:55

	o  Add convenience macros to read from and write to the frame buffer.
	o  Reorder the programming sequence to first program the registers
	   that define the overall operating mode. Then initialize the rest.
	   This just "feels" better. I don't think it matters.
	o  Properly clear the frame buffer. The way the VGA operates, a read
	   is needed to load the 32-bit latch, after which a write actually
	   triggers a write. Writing only doesn't take any effect.

Affected files ...

.. //depot/projects/tty/sys/dev/vga/vga.c#9 edit

Differences ...

==== //depot/projects/tty/sys/dev/vga/vga.c#9 (text+ko) ====

@@ -38,6 +38,10 @@
 #include <dev/vga/vga.h>
 
 /* Convenience macros. */
+#define	MEM_READ(sc, ofs)		\
+	bus_space_read_1(sc->vga_fb.bst, sc->vga_fb.bsh, ofs)
+#define	MEM_WRITE(sc, ofs, val)		\
+	bus_space_write_1(sc->vga_fb.bst, sc->vga_fb.bsh, ofs, val)
 #define	REG_READ(sc, reg)		\
 	bus_space_read_1(sc->vga_reg.bst, sc->vga_reg.bsh, reg)
 #define	REG_WRITE(sc, reg, val)		\
@@ -57,12 +61,18 @@
 int
 vga_init(struct vga_softc *sc)
 {
+	u_int ofs;
 	uint8_t x;
 
 	/* Make sure the VGA adapter is not in monochrome emulation mode. */
 	x = REG_READ(sc, VGA_GEN_MISC_OUTPUT_R);
 	REG_WRITE(sc, VGA_GEN_MISC_OUTPUT_W, x | VGA_GEN_MO_IOA);
 
+	/* Unprotect CRTC registers 0-7. */
+	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END);
+	x = REG_READ(sc, VGA_CRTC_DATA);
+	REG_WRITE(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR);
+
 	/*
 	 * Wait for the vertical retrace.
 	 * NOTE: this code reads the VGA_GEN_INPUT_STAT_1 register, which has
@@ -84,17 +94,27 @@
 	REG_WRITE(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR);
 
 	/*
-	 * Set the VGA adapter in mode 0x12 (640x480x16).
+	 * Part 1: Reprogram the overall operating mode.
 	 */
 
-	/* Unprotect CRTC registers 0-7. */
-	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END);
-	x = REG_READ(sc, VGA_CRTC_DATA);
-	REG_WRITE(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR);
-
-	/*
-	 * Reprogram the CRTC.
-	 */
+	/* Asynchronous sequencer reset. */
+	REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET);
+	REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR);
+	/* Clock select. */
+	REG_WRITE(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP |
+	    VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA);
+	/* Set sequencer clocking and memory mode. */
+	REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE);
+	REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89);
+	REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE);
+	REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM);
+	/* Set the graphics controller in graphics mode. */
+	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS);
+	REG_WRITE(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA);
+	/* Set the attribute controller in graphics mode. */
+	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL);
+	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_MC_GA);
+	/* Program the CRT controller. */
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL);
 	REG_WRITE(sc, VGA_CRTC_DATA, 0x5f);			/* 760 */
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END);
@@ -112,32 +132,16 @@
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OVERFLOW);
 	REG_WRITE(sc, VGA_CRTC_DATA, VGA_CRTC_OF_VT9 | VGA_CRTC_OF_LC8 |
 	    VGA_CRTC_OF_VBS8 | VGA_CRTC_OF_VRS8 | VGA_CRTC_OF_VDE8);
-	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN);
-	REG_WRITE(sc, VGA_CRTC_DATA, 0);
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MAX_SCAN_LINE);
 	REG_WRITE(sc, VGA_CRTC_DATA, VGA_CRTC_MSL_LC9);
-	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START);
-	REG_WRITE(sc, VGA_CRTC_DATA, 0);
-	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END);
-	REG_WRITE(sc, VGA_CRTC_DATA, 0);
-	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH);
-	REG_WRITE(sc, VGA_CRTC_DATA, 0);
-	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW);
-	REG_WRITE(sc, VGA_CRTC_DATA, 0);
-	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH);
-	REG_WRITE(sc, VGA_CRTC_DATA, 0);
-	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW);
-	REG_WRITE(sc, VGA_CRTC_DATA, 0x59);
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_START);
 	REG_WRITE(sc, VGA_CRTC_DATA, 0xea);			/* 480 + 10 */
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END);
-	REG_WRITE(sc, VGA_CRTC_DATA, 0x8c);
+	REG_WRITE(sc, VGA_CRTC_DATA, 0x0c);
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_DISPLAY_END);
 	REG_WRITE(sc, VGA_CRTC_DATA, 0xdf);			/* 480 - 1*/
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OFFSET);
 	REG_WRITE(sc, VGA_CRTC_DATA, 0x28);
-	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC);
-	REG_WRITE(sc, VGA_CRTC_DATA, 0);
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_VERT_BLANK);
 	REG_WRITE(sc, VGA_CRTC_DATA, 0xe7);			/* 480 + 7 */
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_VERT_BLANK);
@@ -147,34 +151,55 @@
 	    VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS);
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE);
 	REG_WRITE(sc, VGA_CRTC_DATA, 0xff);			/* 480 + 31 */
+	/* Re-enable the sequencer. */
+	REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET);
+	REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR);
 
 	/*
-	 * Reprogram the general registers.
+	 * Part 2: Reprogram the remaining registers.
 	 */
-	REG_WRITE(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP |
-	    VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA);
 	REG_WRITE(sc, VGA_GEN_FEATURE_CTRL_W, 0);
 
-	/*
-	 * Reprogram the sequencer.
-	 */
-	REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET);
-	REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR);
-	REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE);
-	REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89);
 	REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK);
 	REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 |
 	    VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0);
 	REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT);
 	REG_WRITE(sc, VGA_SEQ_DATA, 0);
-	REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE);
-	REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM);
+
+	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN);
+	REG_WRITE(sc, VGA_CRTC_DATA, 0);
+	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START);
+	REG_WRITE(sc, VGA_CRTC_DATA, 0);
+	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END);
+	REG_WRITE(sc, VGA_CRTC_DATA, 0);
+	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH);
+	REG_WRITE(sc, VGA_CRTC_DATA, 0);
+	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW);
+	REG_WRITE(sc, VGA_CRTC_DATA, 0);
+	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH);
+	REG_WRITE(sc, VGA_CRTC_DATA, 0);
+	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW);
+	REG_WRITE(sc, VGA_CRTC_DATA, 0x59);
+	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC);
+	REG_WRITE(sc, VGA_CRTC_DATA, 0);
+
+	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
+	REG_WRITE(sc, VGA_GC_DATA, 0);
+	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET);
+	REG_WRITE(sc, VGA_GC_DATA, 0);
+	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE);
+	REG_WRITE(sc, VGA_GC_DATA, 0);
+	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE);
+	REG_WRITE(sc, VGA_GC_DATA, 0);
+	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT);
+	REG_WRITE(sc, VGA_GC_DATA, 0);
+	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
+	REG_WRITE(sc, VGA_GC_DATA, 0);
+	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE);
+	REG_WRITE(sc, VGA_GC_DATA, 0x0f);
+	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK);
+	REG_WRITE(sc, VGA_GC_DATA, 0xff);
 
-	/*
-	 * Reprogram the attribute controller. The internal flip-flop is
-	 * known to be clear and the next first will be to the address
-	 * register.
-	 */
 	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(0));
 	REG_WRITE(sc, VGA_AC_WRITE, 0);
 	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(1));
@@ -215,8 +240,6 @@
 	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(15));
 	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
 	    VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B);
-	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL);
-	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_MC_GA);
 	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_OVERSCAN_COLOR);
 	REG_WRITE(sc, VGA_AC_WRITE, 0);
 	REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_COLOR_PLANE_ENABLE);
@@ -227,32 +250,13 @@
 	REG_WRITE(sc, VGA_AC_WRITE, 0);
 
 	/*
-	 * Reprogram the graphics controller.
-	 */
-	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
-	REG_WRITE(sc, VGA_GC_DATA, 0);
-	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET);
-	REG_WRITE(sc, VGA_GC_DATA, 0);
-	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE);
-	REG_WRITE(sc, VGA_GC_DATA, 0);
-	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE);
-	REG_WRITE(sc, VGA_GC_DATA, 0);
-	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT);
-	REG_WRITE(sc, VGA_GC_DATA, 0);
-	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
-	REG_WRITE(sc, VGA_GC_DATA, 0);
-	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS);
-	REG_WRITE(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA);
-	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE);
-	REG_WRITE(sc, VGA_GC_DATA, 0x0f);
-	REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK);
-	REG_WRITE(sc, VGA_GC_DATA, 0xff);
-
-	/*
 	 * Done. Clear the frame buffer. All bit planes are enabled, so
-	 * a single write should clear all planes.
+	 * a single-paged loop should clear all planes.
 	 */
-	bus_space_set_multi_1(sc->vga_fb.bst, sc->vga_fb.bsh, 0, 0, 65536);
+	for (ofs = 0; ofs < 38400; ofs++) {
+		MEM_READ(sc, ofs);
+		MEM_WRITE(sc, ofs, 0);
+	}
 
 	/* Re-enable the sync signals. */
 	REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200505100538.j4A5cZdX040914>