Date: Wed, 16 Apr 1997 16:07:28 -0600 From: Steve Passe <smp@csn.net> To: Michael Searle <searle@longacre.demon.co.uk> Cc: freebsd-hardware@FreeBSD.ORG, smp@FreeBSD.ORG Subject: Re: SMP question. Message-ID: <199704162207.QAA18500@Ilsa.StevesCafe.com> In-Reply-To: Your message of "Wed, 16 Apr 1997 20:14:07 -0000." <m7BDBDDAD@longacre.demon.co.uk>
next in thread | previous in thread | raw e-mail | index | archive | help
Hi, > ... > > there is some possibility that the P-90 (I assumme you mean P5-90) will > > be a problem. That vintage of P5 is from the days when the APIC section > > was somewhat unstable, and often required a "matched pair" of CPUs, ie 2 > > from the same stepping and rev level. > > Is this ever necessary for a 2 or 4 P6-150? it is generally believed that this is NOT a problem with any of the P6 chips, but I can't guarantee it. you might also consider trying to clock the P5-150s at 166mHz, the bus will then run @ 66mHz instead of 60mHz. I just purchased a dual P6 with 2 P6-166mHzx512k cache and am successfully running them at 200mHz. -- Steve Passe | powered by smp@csn.net | Symmetric MultiProcessor FreeBSD
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199704162207.QAA18500>