From owner-p4-projects@FreeBSD.ORG Sat Aug 16 18:17:22 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 150A51065671; Sat, 16 Aug 2008 18:17:22 +0000 (UTC) Delivered-To: perforce@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C97E0106566C for ; Sat, 16 Aug 2008 18:17:21 +0000 (UTC) (envelope-from thioretic@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id AC3098FC21 for ; Sat, 16 Aug 2008 18:17:21 +0000 (UTC) (envelope-from thioretic@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.2/8.14.2) with ESMTP id m7GIHLeM055194 for ; Sat, 16 Aug 2008 18:17:21 GMT (envelope-from thioretic@FreeBSD.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.2/8.14.1/Submit) id m7GIHKEV055192 for perforce@freebsd.org; Sat, 16 Aug 2008 18:17:20 GMT (envelope-from thioretic@FreeBSD.org) Date: Sat, 16 Aug 2008 18:17:20 GMT Message-Id: <200808161817.m7GIHKEV055192@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to thioretic@FreeBSD.org using -f From: Maxim Zhuravlev To: Perforce Change Reviews Cc: Subject: PERFORCE change 147578 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Aug 2008 18:17:22 -0000 http://perforce.freebsd.org/chv.cgi?CH=147578 Change 147578 by thioretic@thioretic on 2008/08/16 18:16:53 Integrate from parent. Affected files ... .. //depot/projects/soc2007/thioretic_gidl/amd64/amd64/amd64_mem.c#2 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/amd64/busdma_machdep.c#2 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/amd64/machdep.c#5 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/amd64/mem.c#2 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/conf/GENERIC#3 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/conf/NOTES#4 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/ia32/ia32_signal.c#2 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/include/clock.h#2 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/include/pc/bios.h#2 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/include/specialreg.h#3 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/include/vmparam.h#2 integrate .. //depot/projects/soc2007/thioretic_gidl/amd64/isa/clock.c#4 integrate .. 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//depot/projects/soc2007/thioretic_gidl/xdr/xdr_array.c#1 branch .. //depot/projects/soc2007/thioretic_gidl/xdr/xdr_mbuf.c#1 branch .. //depot/projects/soc2007/thioretic_gidl/xdr/xdr_mem.c#1 branch .. //depot/projects/soc2007/thioretic_gidl/xdr/xdr_reference.c#1 branch .. //depot/projects/soc2007/thioretic_gidl/xdr/xdr_sizeof.c#1 branch Differences ... ==== //depot/projects/soc2007/thioretic_gidl/amd64/amd64/amd64_mem.c#2 (text+ko) ==== @@ -25,7 +25,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/amd64/amd64/amd64_mem.c,v 1.25 2004/08/07 06:21:37 scottl Exp $"); +__FBSDID("$FreeBSD: src/sys/amd64/amd64/amd64_mem.c,v 1.25.8.3 2008/03/19 16:37:23 jhb Exp $"); #include #include @@ -47,31 +47,31 @@ static char *mem_owner_bios = "BIOS"; -#define MR686_FIXMTRR (1<<0) +#define MR686_FIXMTRR (1<<0) -#define mrwithin(mr, a) \ - (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len))) -#define mroverlap(mra, mrb) \ - (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base)) +#define mrwithin(mr, a) \ + (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len))) +#define mroverlap(mra, mrb) \ + (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base)) -#define mrvalid(base, len) \ - ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */ \ - ((len) >= (1 << 12)) && /* length is >= 4k */ \ - powerof2((len)) && /* ... and power of two */ \ - !((base) & ((len) - 1))) /* range is not discontiuous */ +#define mrvalid(base, len) \ + ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */ \ + ((len) >= (1 << 12)) && /* length is >= 4k */ \ + powerof2((len)) && /* ... and power of two */ \ + !((base) & ((len) - 1))) /* range is not discontiuous */ -#define mrcopyflags(curr, new) (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK)) +#define mrcopyflags(curr, new) \ + (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK)) -static int mtrrs_disabled; +static int mtrrs_disabled; TUNABLE_INT("machdep.disable_mtrrs", &mtrrs_disabled); SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN, - &mtrrs_disabled, 0, "Disable amd64 MTRRs."); + &mtrrs_disabled, 0, "Disable amd64 MTRRs."); -static void amd64_mrinit(struct mem_range_softc *sc); -static int amd64_mrset(struct mem_range_softc *sc, - struct mem_range_desc *mrd, - int *arg); -static void amd64_mrAPinit(struct mem_range_softc *sc); +static void amd64_mrinit(struct mem_range_softc *sc); +static int amd64_mrset(struct mem_range_softc *sc, + struct mem_range_desc *mrd, int *arg); +static void amd64_mrAPinit(struct mem_range_softc *sc); static struct mem_range_ops amd64_mrops = { amd64_mrinit, @@ -80,157 +80,159 @@ }; /* XXX for AP startup hook */ -static u_int64_t mtrrcap, mtrrdef; +static u_int64_t mtrrcap, mtrrdef; + +/* The bitmask for the PhysBase and PhysMask fields of the variable MTRRs. */ +static u_int64_t mtrr_physmask; -static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc, - struct mem_range_desc *mrd); -static void amd64_mrfetch(struct mem_range_softc *sc); -static int amd64_mtrrtype(int flags); -static int amd64_mrt2mtrr(int flags, int oldval); -static int amd64_mtrrconflict(int flag1, int flag2); -static void amd64_mrstore(struct mem_range_softc *sc); -static void amd64_mrstoreone(void *arg); -static struct mem_range_desc *amd64_mtrrfixsearch(struct mem_range_softc *sc, - u_int64_t addr); -static int amd64_mrsetlow(struct mem_range_softc *sc, - struct mem_range_desc *mrd, - int *arg); -static int amd64_mrsetvariable(struct mem_range_softc *sc, - struct mem_range_desc *mrd, - int *arg); +static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc, + struct mem_range_desc *mrd); +static void amd64_mrfetch(struct mem_range_softc *sc); +static int amd64_mtrrtype(int flags); +static int amd64_mrt2mtrr(int flags, int oldval); +static int amd64_mtrrconflict(int flag1, int flag2); +static void amd64_mrstore(struct mem_range_softc *sc); +static void amd64_mrstoreone(void *arg); +static struct mem_range_desc *amd64_mtrrfixsearch(struct mem_range_softc *sc, + u_int64_t addr); +static int amd64_mrsetlow(struct mem_range_softc *sc, + struct mem_range_desc *mrd, int *arg); +static int amd64_mrsetvariable(struct mem_range_softc *sc, + struct mem_range_desc *mrd, int *arg); /* amd64 MTRR type to memory range type conversion */ static int amd64_mtrrtomrt[] = { - MDF_UNCACHEABLE, - MDF_WRITECOMBINE, - MDF_UNKNOWN, - MDF_UNKNOWN, - MDF_WRITETHROUGH, - MDF_WRITEPROTECT, - MDF_WRITEBACK + MDF_UNCACHEABLE, + MDF_WRITECOMBINE, + MDF_UNKNOWN, + MDF_UNKNOWN, + MDF_WRITETHROUGH, + MDF_WRITEPROTECT, + MDF_WRITEBACK }; -#define MTRRTOMRTLEN (sizeof(amd64_mtrrtomrt) / sizeof(amd64_mtrrtomrt[0])) - -/* - * Used in /dev/mem drivers and elsewhere - */ -MALLOC_DEFINE(M_MEMDESC, "memdesc", "memory range descriptors"); +#define MTRRTOMRTLEN (sizeof(amd64_mtrrtomrt) / sizeof(amd64_mtrrtomrt[0])) static int amd64_mtrr2mrt(int val) { + if (val < 0 || val >= MTRRTOMRTLEN) - return MDF_UNKNOWN; - return amd64_mtrrtomrt[val]; + return (MDF_UNKNOWN); + return (amd64_mtrrtomrt[val]); } -/* +/* * amd64 MTRR conflicts. Writeback and uncachable may overlap. */ static int amd64_mtrrconflict(int flag1, int flag2) { + flag1 &= MDF_ATTRMASK; flag2 &= MDF_ATTRMASK; if ((flag1 & MDF_UNKNOWN) || (flag2 & MDF_UNKNOWN)) - return 1; + return (1); if (flag1 == flag2 || (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) || (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE)) - return 0; - return 1; + return (0); + return (1); } /* * Look for an exactly-matching range. */ static struct mem_range_desc * -mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd) +mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd) { - struct mem_range_desc *cand; - int i; - - for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++) - if ((cand->mr_base == mrd->mr_base) && - (cand->mr_len == mrd->mr_len)) - return(cand); - return(NULL); + struct mem_range_desc *cand; + int i; + + for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++) + if ((cand->mr_base == mrd->mr_base) && + (cand->mr_len == mrd->mr_len)) + return (cand); + return (NULL); } /* - * Fetch the current mtrr settings from the current CPU (assumed to all - * be in sync in the SMP case). Note that if we are here, we assume - * that MTRRs are enabled, and we may or may not have fixed MTRRs. + * Fetch the current mtrr settings from the current CPU (assumed to + * all be in sync in the SMP case). Note that if we are here, we + * assume that MTRRs are enabled, and we may or may not have fixed + * MTRRs. */ static void amd64_mrfetch(struct mem_range_softc *sc) { - struct mem_range_desc *mrd; - u_int64_t msrv; - int i, j, msr; + struct mem_range_desc *mrd; + u_int64_t msrv; + int i, j, msr; - mrd = sc->mr_desc; + mrd = sc->mr_desc; - /* Get fixed-range MTRRs */ - if (sc->mr_cap & MR686_FIXMTRR) { - msr = MSR_MTRR64kBase; - for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { - msrv = rdmsr(msr); - for (j = 0; j < 8; j++, mrd++) { - mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | - amd64_mtrr2mrt(msrv & 0xff) | - MDF_ACTIVE; - if (mrd->mr_owner[0] == 0) - strcpy(mrd->mr_owner, mem_owner_bios); - msrv = msrv >> 8; - } + /* Get fixed-range MTRRs. */ + if (sc->mr_cap & MR686_FIXMTRR) { + msr = MSR_MTRR64kBase; + for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { + msrv = rdmsr(msr); + for (j = 0; j < 8; j++, mrd++) { + mrd->mr_flags = + (mrd->mr_flags & ~MDF_ATTRMASK) | + amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE; + if (mrd->mr_owner[0] == 0) + strcpy(mrd->mr_owner, mem_owner_bios); + msrv = msrv >> 8; + } + } + msr = MSR_MTRR16kBase; + for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { + msrv = rdmsr(msr); + for (j = 0; j < 8; j++, mrd++) { + mrd->mr_flags = + (mrd->mr_flags & ~MDF_ATTRMASK) | + amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE; + if (mrd->mr_owner[0] == 0) + strcpy(mrd->mr_owner, mem_owner_bios); + msrv = msrv >> 8; + } + } + msr = MSR_MTRR4kBase; + for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { + msrv = rdmsr(msr); + for (j = 0; j < 8; j++, mrd++) { + mrd->mr_flags = + (mrd->mr_flags & ~MDF_ATTRMASK) | + amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE; + if (mrd->mr_owner[0] == 0) + strcpy(mrd->mr_owner, mem_owner_bios); + msrv = msrv >> 8; + } + } } - msr = MSR_MTRR16kBase; - for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { - msrv = rdmsr(msr); - for (j = 0; j < 8; j++, mrd++) { + + /* Get remainder which must be variable MTRRs. */ + msr = MSR_MTRRVarBase; + for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { + msrv = rdmsr(msr); mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | - amd64_mtrr2mrt(msrv & 0xff) | - MDF_ACTIVE; - if (mrd->mr_owner[0] == 0) - strcpy(mrd->mr_owner, mem_owner_bios); - msrv = msrv >> 8; - } + amd64_mtrr2mrt(msrv & MTRR_PHYSBASE_TYPE); + mrd->mr_base = msrv & mtrr_physmask; + msrv = rdmsr(msr + 1); + mrd->mr_flags = (msrv & MTRR_PHYSMASK_VALID) ? + (mrd->mr_flags | MDF_ACTIVE) : + (mrd->mr_flags & ~MDF_ACTIVE); + + /* Compute the range from the mask. Ick. */ + mrd->mr_len = (~(msrv & mtrr_physmask) & + (mtrr_physmask | 0xfffL)) + 1; + if (!mrvalid(mrd->mr_base, mrd->mr_len)) + mrd->mr_flags |= MDF_BOGUS; + + /* If unclaimed and active, must be the BIOS. */ + if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0)) + strcpy(mrd->mr_owner, mem_owner_bios); } - msr = MSR_MTRR4kBase; - for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { - msrv = rdmsr(msr); - for (j = 0; j < 8; j++, mrd++) { - mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | - amd64_mtrr2mrt(msrv & 0xff) | - MDF_ACTIVE; - if (mrd->mr_owner[0] == 0) - strcpy(mrd->mr_owner, mem_owner_bios); - msrv = msrv >> 8; - } - } - } - - /* Get remainder which must be variable MTRRs */ - msr = MSR_MTRRVarBase; - for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { - msrv = rdmsr(msr); - mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) | - amd64_mtrr2mrt(msrv & 0xff); - mrd->mr_base = msrv & 0x000000fffffff000L; - msrv = rdmsr(msr + 1); - mrd->mr_flags = (msrv & 0x800) ? - (mrd->mr_flags | MDF_ACTIVE) : - (mrd->mr_flags & ~MDF_ACTIVE); - /* Compute the range from the mask. Ick. */ - mrd->mr_len = (~(msrv & 0x000000fffffff000L) & 0x000000ffffffffffL) + 1; - if (!mrvalid(mrd->mr_base, mrd->mr_len)) - mrd->mr_flags |= MDF_BOGUS; - /* If unclaimed and active, must be the BIOS */ - if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0)) - strcpy(mrd->mr_owner, mem_owner_bios); - } } /* @@ -239,17 +241,17 @@ static int amd64_mtrrtype(int flags) { - int i; + int i; - flags &= MDF_ATTRMASK; + flags &= MDF_ATTRMASK; - for (i = 0; i < MTRRTOMRTLEN; i++) { - if (amd64_mtrrtomrt[i] == MDF_UNKNOWN) - continue; - if (flags == amd64_mtrrtomrt[i]) - return(i); - } - return(-1); + for (i = 0; i < MTRRTOMRTLEN; i++) { + if (amd64_mtrrtomrt[i] == MDF_UNKNOWN) + continue; + if (flags == amd64_mtrrtomrt[i]) + return (i); + } + return (-1); } static int @@ -258,8 +260,8 @@ int val; if ((val = amd64_mtrrtype(flags)) == -1) - return oldval & 0xff; - return val & 0xff; + return (oldval & 0xff); + return (val & 0xff); } /* @@ -272,105 +274,124 @@ amd64_mrstore(struct mem_range_softc *sc) { #ifdef SMP - /* - * We should use ipi_all_but_self() to call other CPUs into a - * locking gate, then call a target function to do this work. - * The "proper" solution involves a generalised locking gate - * implementation, not ready yet. - */ - smp_rendezvous(NULL, amd64_mrstoreone, NULL, (void *)sc); + /* + * We should use ipi_all_but_self() to call other CPUs into a + * locking gate, then call a target function to do this work. + * The "proper" solution involves a generalised locking gate + * implementation, not ready yet. + */ + smp_rendezvous(NULL, amd64_mrstoreone, NULL, sc); #else - disable_intr(); /* disable interrupts */ - amd64_mrstoreone((void *)sc); - enable_intr(); + disable_intr(); /* disable interrupts */ + amd64_mrstoreone(sc); + enable_intr(); #endif } /* * Update the current CPU's MTRRs with those represented in the - * descriptor list. Note that we do this wholesale rather than - * just stuffing one entry; this is simpler (but slower, of course). + * descriptor list. Note that we do this wholesale rather than just + * stuffing one entry; this is simpler (but slower, of course). */ static void amd64_mrstoreone(void *arg) { - struct mem_range_softc *sc = (struct mem_range_softc *)arg; - struct mem_range_desc *mrd; - u_int64_t omsrv, msrv; - int i, j, msr; - u_int cr4save; + struct mem_range_softc *sc = arg; + struct mem_range_desc *mrd; + u_int64_t omsrv, msrv; + int i, j, msr; + u_int cr4save; + + mrd = sc->mr_desc; + + /* Disable PGE. */ + cr4save = rcr4(); + if (cr4save & CR4_PGE) + load_cr4(cr4save & ~CR4_PGE); + + /* Disable caches (CD = 1, NW = 0). */ + load_cr0((rcr0() & ~CR0_NW) | CR0_CD); - mrd = sc->mr_desc; + /* Flushes caches and TLBs. */ + wbinvd(); - cr4save = rcr4(); /* save cr4 */ - if (cr4save & CR4_PGE) - load_cr4(cr4save & ~CR4_PGE); - load_cr0((rcr0() & ~CR0_NW) | CR0_CD); /* disable caches (CD = 1, NW = 0) */ - wbinvd(); /* flush caches, TLBs */ - wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800); /* disable MTRRs (E = 0) */ + /* Disable MTRRs (E = 0). */ + wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE); - /* Set fixed-range MTRRs */ - if (sc->mr_cap & MR686_FIXMTRR) { - msr = MSR_MTRR64kBase; - for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { - msrv = 0; - omsrv = rdmsr(msr); - for (j = 7; j >= 0; j--) { - msrv = msrv << 8; - msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); - } - wrmsr(msr, msrv); - mrd += 8; + /* Set fixed-range MTRRs. */ + if (sc->mr_cap & MR686_FIXMTRR) { + msr = MSR_MTRR64kBase; + for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { + msrv = 0; + omsrv = rdmsr(msr); + for (j = 7; j >= 0; j--) { + msrv = msrv << 8; + msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, + omsrv >> (j * 8)); + } + wrmsr(msr, msrv); + mrd += 8; + } + msr = MSR_MTRR16kBase; + for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { + msrv = 0; + omsrv = rdmsr(msr); + for (j = 7; j >= 0; j--) { + msrv = msrv << 8; + msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, + omsrv >> (j * 8)); + } + wrmsr(msr, msrv); + mrd += 8; + } + msr = MSR_MTRR4kBase; + for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { + msrv = 0; + omsrv = rdmsr(msr); + for (j = 7; j >= 0; j--) { + msrv = msrv << 8; + msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, + omsrv >> (j * 8)); + } + wrmsr(msr, msrv); + mrd += 8; + } } - msr = MSR_MTRR16kBase; - for (i = 0; i < (MTRR_N16K / 8); i++, msr++) { - msrv = 0; - omsrv = rdmsr(msr); - for (j = 7; j >= 0; j--) { - msrv = msrv << 8; - msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); - } - wrmsr(msr, msrv); - mrd += 8; + + /* Set remainder which must be variable MTRRs. */ + msr = MSR_MTRRVarBase; + for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { + /* base/type register */ + omsrv = rdmsr(msr); + if (mrd->mr_flags & MDF_ACTIVE) { + msrv = mrd->mr_base & mtrr_physmask; + msrv |= amd64_mrt2mtrr(mrd->mr_flags, omsrv); + } else { + msrv = 0; + } + wrmsr(msr, msrv); + + /* mask/active register */ + if (mrd->mr_flags & MDF_ACTIVE) { + msrv = MTRR_PHYSMASK_VALID | + (~(mrd->mr_len - 1) & mtrr_physmask); + } else { + msrv = 0; + } + wrmsr(msr + 1, msrv); } - msr = MSR_MTRR4kBase; - for (i = 0; i < (MTRR_N4K / 8); i++, msr++) { - msrv = 0; - omsrv = rdmsr(msr); - for (j = 7; j >= 0; j--) { - msrv = msrv << 8; - msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8)); - } - wrmsr(msr, msrv); - mrd += 8; - } - } + + /* Flush caches, TLBs. */ + wbinvd(); + + /* Enable MTRRs. */ + wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE); + + /* Enable caches (CD = 0, NW = 0). */ + load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); - /* Set remainder which must be variable MTRRs */ - msr = MSR_MTRRVarBase; - for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) { - /* base/type register */ - omsrv = rdmsr(msr); - if (mrd->mr_flags & MDF_ACTIVE) { - msrv = mrd->mr_base & 0x000000fffffff000L; - msrv |= amd64_mrt2mtrr(mrd->mr_flags, omsrv); - } else { - msrv = 0; - } - wrmsr(msr, msrv); - - /* mask/active register */ - if (mrd->mr_flags & MDF_ACTIVE) { - msrv = 0x800 | (~(mrd->mr_len - 1) & 0x000000fffffff000L); - } else { - msrv = 0; - } - wrmsr(msr + 1, msrv); - } - wbinvd(); /* flush caches, TLBs */ - wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | 0x800); /* restore MTRR state */ - load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* enable caches CD = 0 and NW = 0 */ - load_cr4(cr4save); /* restore cr4 */ + /* Restore PGE. */ + load_cr4(cr4save); } /* @@ -379,227 +400,260 @@ static struct mem_range_desc * amd64_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr) { - struct mem_range_desc *mrd; - int i; - - for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K); i++, mrd++) - if ((addr >= mrd->mr_base) && (addr < (mrd->mr_base + mrd->mr_len))) - return(mrd); - return(NULL); + struct mem_range_desc *mrd; + int i; + + for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K); + i++, mrd++) + if ((addr >= mrd->mr_base) && + (addr < (mrd->mr_base + mrd->mr_len))) + return (mrd); + return (NULL); } /* - * Try to satisfy the given range request by manipulating the fixed MTRRs that - * cover low memory. + * Try to satisfy the given range request by manipulating the fixed + * MTRRs that cover low memory. * - * Note that we try to be generous here; we'll bloat the range out to the - * next higher/lower boundary to avoid the consumer having to know too much - * about the mechanisms here. + * Note that we try to be generous here; we'll bloat the range out to + * the next higher/lower boundary to avoid the consumer having to know + * too much about the mechanisms here. * - * XXX note that this will have to be updated when we start supporting "busy" ranges. + * XXX note that this will have to be updated when we start supporting + * "busy" ranges. */ static int amd64_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg) { - struct mem_range_desc *first_md, *last_md, *curr_md; + struct mem_range_desc *first_md, *last_md, *curr_md; + + /* Range check. */ + if (((first_md = amd64_mtrrfixsearch(sc, mrd->mr_base)) == NULL) || + ((last_md = amd64_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL)) + return (EINVAL); - /* range check */ - if (((first_md = amd64_mtrrfixsearch(sc, mrd->mr_base)) == NULL) || - ((last_md = amd64_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL)) - return(EINVAL); + /* Check that we aren't doing something risky. */ + if (!(mrd->mr_flags & MDF_FORCE)) + for (curr_md = first_md; curr_md <= last_md; curr_md++) { >>> TRUNCATED FOR MAIL (1000 lines) <<<