Date: Sat, 3 May 2003 19:01:12 -0700 (PDT) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 30505 for review Message-ID: <200305040201.h4421CMu002262@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=30505 Change 30505 by jmallett@jmallett_dalek on 2003/05/03 19:00:53 Drag over DDB support kicking and screaming from NetBSD. This blows up interestingly right now due to the fact I disabled our exception vectors in favor of ARCS which gives information. Working on it. Affected files ... .. //depot/projects/mips/sys/conf/files.mips#17 edit .. //depot/projects/mips/sys/mips/include/cpu.h#11 edit .. //depot/projects/mips/sys/mips/include/db_machdep.h#3 edit .. //depot/projects/mips/sys/mips/include/mips_opcode.h#1 add .. //depot/projects/mips/sys/mips/include/pcb.h#4 edit .. //depot/projects/mips/sys/mips/include/pte.h#3 edit .. //depot/projects/mips/sys/mips/include/setjmp.h#1 add .. //depot/projects/mips/sys/mips/include/trap.h#1 add .. //depot/projects/mips/sys/mips/mips/db_disasm.c#1 add .. //depot/projects/mips/sys/mips/mips/db_hwwatch.c#1 add .. //depot/projects/mips/sys/mips/mips/db_interface.c#1 add .. //depot/projects/mips/sys/mips/mips/db_trace.c#1 add .. //depot/projects/mips/sys/mips/mips/genassym.c#7 edit .. //depot/projects/mips/sys/mips/mips/locore_mips3.S#8 edit Differences ... ==== //depot/projects/mips/sys/conf/files.mips#17 (text+ko) ==== @@ -30,6 +30,11 @@ mips/mips/cache_r5k.c standard mips/mips/cache_r5k_subr.S standard +mips/mips/db_disasm.c optional ddb +mips/mips/db_hwwatch.c optional ddb +mips/mips/db_interface.c optional ddb +mips/mips/db_trace.c optional ddb + # This stanza is platform files, per platform. geom/geom_fx.c optional sgimips mips/sgimips/clock.c optional sgimips ==== //depot/projects/mips/sys/mips/include/cpu.h#11 (text+ko) ==== @@ -120,7 +120,9 @@ extern int cpu_arch; extern int mips_cpu_flags; extern int mips_has_r4k_mmu; +#define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) extern int mips_has_llsc; +#define MIPS_HAS_LLSC (mips_has_llsc) extern int mips3_pg_cached; #define CPU_MIPS_R4K_MMU 0x0001 ==== //depot/projects/mips/sys/mips/include/db_machdep.h#3 (text+ko) ==== @@ -1,5 +1,8 @@ -/*- - * Copyright (c) 2003 Juli Mallett. All rights reserved. +/* $NetBSD: db_machdep.h,v 1.14 2002/03/05 14:12:29 simonb Exp $ */ + +/* + * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author) + * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -9,11 +12,17 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Jonathan Stone for + * the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) @@ -24,17 +33,86 @@ * * $FreeBSD$ */ +#ifndef _MIPS_DB_MACHDEP_H_ +#define _MIPS_DB_MACHDEP_H_ + +#include <machine/frame.h> +#include <machine/trap.h> +#include <machine/reg.h> /* register state */ +#include <machine/regnum.h> /* symbolic register indices */ + + +typedef unsigned long db_addr_t; /* address - unsigned */ +typedef long db_expr_t; /* expression - signed */ + +typedef struct frame db_regs_t; + +extern db_regs_t ddb_regs; /* register state */ +#define DDB_REGS (&ddb_regs) + +#define PC_REGS(regs) ((db_addr_t)(regs)->f_regs[PC]) + +#define PC_ADVANCE(regs) do { \ + if ((db_get_value((regs)->f_regs[PC], sizeof(int), FALSE) & \ + 0xfc00003f) == 0xd) \ + (regs)->f_regs[PC] += BKPT_SIZE; \ +} while(0) + +/* Similar to PC_ADVANCE(), except only advance on cpu_Debugger()'s bpt */ +#define PC_BREAK_ADVANCE(regs) do { \ + if (db_get_value((regs)->f_regs[PC], sizeof(int), FALSE) == 0xd) \ + (regs)->f_regs[PC] += BKPT_SIZE; \ +} while(0) + +#define BKPT_INST 0x0001000D +#define BKPT_SIZE (4) /* size of breakpoint inst */ +#define BKPT_SET(inst) (BKPT_INST) + +#define IS_BREAKPOINT_TRAP(type, code) ((type) == T_BREAK) +#define IS_WATCHPOINT_TRAP(type, code) (0) /* XXX mips3 watchpoint */ + +/* + * Interface to disassembly (shared with mdb) + */ +db_addr_t db_disasm_insn(int insn, db_addr_t loc, boolean_t altfmt); + + +/* + * Entrypoints to DDB for kernel, keyboard drivers, init hook + */ +void kdb_kbd_trap(db_regs_t *); +void db_set_ddb_regs(int type, register_t *); +int kdb_trap(int type, register_t *); + +#define DB_SMALL_VALUE_MAX (0x7fffffff) +#define DB_SMALL_VALUE_MIN (-0x40001) + +/* + * Constants for KGDB. + */ +typedef register_t kgdb_reg_t; +#define KGDB_NUMREGS 90 +#define KGDB_BUFLEN 1024 -#ifndef _MACHINE_DB_MACHDEP_H_ -#define _MACHINE_DB_MACHDEP_H_ +/* + * MIPS cpus have no hardware single-step. + */ +#define SOFTWARE_SSTEP + +#define inst_trap_return(ins) ((ins)&0) -#include <machine/frame.h> +boolean_t inst_branch(int inst); +boolean_t inst_call(int inst); +boolean_t inst_return(int inst); +boolean_t inst_load(int inst); +boolean_t inst_store(int inst); +boolean_t inst_unconditional_flow_transfer(int inst); +db_addr_t branch_taken(int inst, db_addr_t pc, db_regs_t *regs); +db_addr_t next_instr_address(db_addr_t pc, boolean_t bd); /* - * Machine-dependent definitions for the new kernel debugger. + * We have machine-dependent commands. */ -typedef vm_offset_t db_addr_t; -typedef long db_expr_t; -typedef struct trapframe db_regs_t; +#define DB_MACHINE_COMMANDS -#endif /* !_MACHINE_DB_MACHDEP_H_ */ +#endif /* _MIPS_DB_MACHDEP_H_ */ ==== //depot/projects/mips/sys/mips/include/pcb.h#4 (text+ko) ==== @@ -35,10 +35,14 @@ */ struct pcb { struct fpreg pcb_fpregs; /* Saved floating point registers */ - struct reg pcb_regs; /* Saved regs. XXX This is excessive. */ + register_t pcb_context[12]; /* kernel context for resume */ + char *pcb_onfault; /* for copyin/copyout faults */ + u_int32_t pcb_ppl; /* previous priority level */ }; #ifdef _KERNEL +#define PCB_FSR(pcb) ((pcb)->pcb_fpregs.r_regs[FSR - FPBASE]) + int savectx(struct pcb *pcb); #endif ==== //depot/projects/mips/sys/mips/include/pte.h#3 (text+ko) ==== @@ -176,10 +176,10 @@ #define mips3_pfn_is_ext(x) ((x) & 0x3c000000) #define mips3_paddr_to_tlbpfn(x) \ - (((paddr_t)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) + (((vm_paddr_t)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) #define mips3_tlbpfn_to_paddr(x) \ - ((paddr_t)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) -#define mips3_vad_to_vpn(x) ((vaddr_t)(x) & MIPS3_PG_SVPN) + ((vm_paddr_t)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) +#define mips3_vad_to_vpn(x) ((vm_offset_t)(x) & MIPS3_PG_SVPN) #define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN) #define MIPS3_PTE_TO_PADDR(pte) (mips3_tlbpfn_to_paddr(pte)) @@ -224,7 +224,7 @@ #define PTE_TO_PADDR(pte) MIPS3_PTE_TO_PADDR((pte)) #define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va)) -#define mips_tlbpfn_to_paddr(x) mips3_tlbpfn_to_paddr((vaddr_t)(x)) +#define mips_tlbpfn_to_paddr(x) mips3_tlbpfn_to_paddr((vm_offset_t)(x)) #define mips_paddr_to_tlbpfn(x) mips3_paddr_to_tlbpfn((x)) #endif /* ! LOCORE */ @@ -234,7 +234,7 @@ * Kernel virtual address to page table entry and visa versa. */ #define kvtopte(va) \ - (kptemap + (((vaddr_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT)) + (kptemap + (((vm_offset_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT)) #define ptetokv(pte) \ ((((pt_entry_t *)(pte) - kptemap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) ==== //depot/projects/mips/sys/mips/mips/genassym.c#7 (text+ko) ==== @@ -39,6 +39,7 @@ #include <vm/vm_map.h> #include <machine/locore.h> +#include <machine/reg.h> ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread)); ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb)); @@ -173,6 +174,20 @@ ASSYM(TF_REG_EPC, offsetof(struct trapframe, tf_regs[TF_EPC])); ASSYM(TF_PPL, offsetof(struct trapframe, tf_ppl)); +ASSYM(CTXSWFRAME_SIZ, sizeof(label_t)); +ASSYM(SF_REG_SR, offsetof(label_t, val[11])); +ASSYM(SF_REG_RA, offsetof(label_t, val[10])); +ASSYM(SF_REG_S0, offsetof(label_t, val[0])); +ASSYM(SF_REG_S1, offsetof(label_t, val[1])); +ASSYM(SF_REG_S2, offsetof(label_t, val[2])); +ASSYM(SF_REG_S3, offsetof(label_t, val[3])); +ASSYM(SF_REG_S4, offsetof(label_t, val[4])); +ASSYM(SF_REG_S5, offsetof(label_t, val[5])); +ASSYM(SF_REG_S6, offsetof(label_t, val[6])); +ASSYM(SF_REG_S7, offsetof(label_t, val[7])); +ASSYM(SF_REG_SP, offsetof(label_t, val[8])); +ASSYM(SF_REG_S8, offsetof(label_t, val[9])); + ASSYM(VM_MIN_ADDRESS, VM_MIN_ADDRESS); ASSYM(VM_MAXUSER_ADDRESS, VM_MAXUSER_ADDRESS); ASSYM(VM_MAX_ADDRESS, VM_MAX_ADDRESS); ==== //depot/projects/mips/sys/mips/mips/locore_mips3.S#8 (text+ko) ==== @@ -87,6 +87,8 @@ * $FreeBSD$ */ +#include "opt_ddb.h" + #include <sys/cdefs.h> #include <machine/asm.h> @@ -459,3 +461,47 @@ #endif #endif END(mips_maybewait_idle) + +#if defined(DDB) || defined(KGDB) +/* + * setjmp(label_t *) + * longjmp(label_t *) + */ +LEAF(setjmp) + mfc0 v0, MIPS_COP_0_STATUS + REG_S s0, SF_REG_S0(a0) + REG_S s1, SF_REG_S1(a0) + REG_S s2, SF_REG_S2(a0) + REG_S s3, SF_REG_S3(a0) + REG_S s4, SF_REG_S4(a0) + REG_S s5, SF_REG_S5(a0) + REG_S s6, SF_REG_S6(a0) + REG_S s7, SF_REG_S7(a0) + REG_S sp, SF_REG_SP(a0) + REG_S s8, SF_REG_S8(a0) + REG_S ra, SF_REG_RA(a0) + REG_S v0, SF_REG_SR(a0) + j ra + move v0, zero +END(setjmp) + +LEAF(longjmp) + REG_L v0, SF_REG_SR(a0) + DYNAMIC_STATUS_MASK(v0,ra) # machine dependent masking + REG_L ra, SF_REG_RA(a0) + REG_L s0, SF_REG_S0(a0) + REG_L s1, SF_REG_S1(a0) + REG_L s2, SF_REG_S2(a0) + REG_L s3, SF_REG_S3(a0) + REG_L s4, SF_REG_S4(a0) + REG_L s5, SF_REG_S5(a0) + REG_L s6, SF_REG_S6(a0) + REG_L s7, SF_REG_S7(a0) + REG_L sp, SF_REG_SP(a0) + REG_L s8, SF_REG_S8(a0) + mtc0 v0, MIPS_COP_0_STATUS + COP0_SYNC + j ra + li v0, 1 +END(longjmp) +#endif
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