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To: dg@Root.COM
Cc: kato@eclogite.eps.nagoya-u.ac.jp, current@FreeBSD.org
Subject: Re: patch for Cyrix/Ti 486SLC/DLC CPU bug 
In-Reply-To: Your message of "Wed, 11 Sep 1996 05:42:29 -0700"
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Date: Thu, 12 Sep 1996 00:32:10 +0900
From: KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
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On Wed, 11 Sep 1996 05:42:29 -0700, David Greenman <dg@Root.COM> said:

>    Your patch changes the page fault exception to an interrupt gate, not the 
> FPU exception, but I understand what you meant.

Sorry, I was mistaken.  The patch changes PAGE FAULT exception to
interrupt gate to inhibit interruption (c.f. bellow).


>    I'd be interested to hear more about why this is required. The register
> should contain only the information about the last exception - and there
> shouldn't be any opportunity to trap again while in trap() before it is read.

CR2 might be modified by hardware interruption before it is read.  The
contributor of the trap.c modification observed:

   1: CR2 register equals to 0 when it is read in trap_pfault().
   2: The core dump shows CR2 should not be 0.
   3: He change trap gate into interrupt gate, CR2 shows correct
      address.

These observation imply the interruption breaks CR2.  This is the
reason for the modification in machdep.c.


> >   3)  The functions pmap_update_{1,2}pg don't use LMSW instruction
> >       but call pmap_update in cpufunc.h (pmap.c).
> 
>    Is this because the Cyrix chip doesn't support selective TLB updates?

Sorry, I lost Cyrix's data book and I couldn't check official
information.  I think Cyrix chip supports selective TLB update, but it 
may have bug and LMSW instruction fails in some cases.  I think this
depends on the version of CPU because some Cyrix machines works without 
pmap.c change.

----
KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
Dept. Earth Planet. Sci., Nagoya Univ.,  Nagoya, 464-01, Japan