Date: Sat, 17 Aug 1996 17:20:35 +0200 (MET DST) From: Thomas Sparrevohn <staff@kyklopen.ping.dk> To: freebsd-current@freebsd.org Subject: 82439HX registerdump patch Message-ID: <Pine.BSI.3.95.960817171857.2351A-100000@kyklopen>
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I just finished writing the registerdump for the 82439HX (Triton II)
chipset. Would anyone with a Triton II based motherboard help me
test it.
Best Regards
Thomas
*** pcisupport.c#ctm Thu Aug 15 21:42:23 1996
--- pcisupport.c Sat Aug 17 15:01:16 1996
***************
*** 131,136 ****
--- 131,138 ----
return ("Intel 82437 (Triton) PCI cache memory controller");
case 0x122e8086:
return ("Intel 82371 (Triton) PCI-ISA bridge");
+ case 0x12508086:
+ return ("Intel 82439HX (Triton II) PCI cache memory controller");
case 0x04961039:
return ("SiS 85c496");
case 0x04061039:
***************
*** 463,468 ****
--- 465,560 ----
{ 0 }
};
+ static const struct condmsg conf82439hx[] =
+ {
+ /* PCON -- PCI Control Register */
+ { 0x00, 0x00, 0x00, M_TR, "\tDRAM ECC/Parity:" },
+ { 0x50, 0x80, 0x80, M_EQ, " ECC" },
+ { 0x50, 0x80, 0x00, M_EQ, " Parity" },
+ { 0x00, 0x00, 0x00, M_TR, ", ECC Test " },
+ { 0x50, 0x40, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tShutdown to Port 92 " },
+ { 0x50, 0x20, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ", Dual Processor NA# " },
+ { 0x50, 0x10, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tPeer Concurrency " },
+ { 0x50, 0x08, 0x00, M_EN, 0 },
+ /* XXX I am not sure thats the SERR# output type is usefull */
+ { 0x00, 0x00, 0x00, M_TR, ", SERR# Output Type:" },
+ { 0x50, 0x04, 0x04, M_EQ, " Normal output" },
+ { 0x50, 0x04, 0x00, M_EQ, " Open drain output" },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tGlobal TXC " },
+ { 0x50, 0x01, 0x00, M_EN, 0 },
+
+ /* CC -- Cache Control Regsiter */
+ { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
+ { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
+ { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
+ { 0x52, 0xc0, 0x00, M_EQ, " NO" },
+ { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
+ { 0x52, 0x30, 0x10, M_EQ, " reserved" },
+ { 0x52, 0x30, 0x20, M_EQ, " reserved" },
+ { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
+ { 0x00, 0x00, 0x00, M_TR, ", NA Disable: " },
+ { 0x52, 0x04, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tExtended Cacheability " },
+ { 0x52, 0x04, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ", SCFMI "},
+ { 0x52, 0x02, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ", L1 " },
+ { 0x52, 0x01, 0x00, M_EN, 0 },
+
+ /* DRAMEC -- DRAM Extended Control Register */
+ { 0x00, 0x00, 0x00, M_TR, "\n\tSpeculative Leadoff " },
+ { 0x56, 0x10, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ", Turn-around Insertion " },
+ { 0x56, 0x08, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tMemory Address Drive Strength: " },
+ { 0x56, 0x06, 0x00, M_EQ, "8mA/8mA" },
+ { 0x56, 0x06, 0x02, M_EQ, "8mA/12mA" },
+ { 0x56, 0x06, 0x04, M_EQ, "12mA/8mA" },
+ { 0x56, 0x06, 0x06, M_EQ, "12mA/12mA" },
+ { 0x00, 0x00, 0x00, M_TR, ", 64 Mbit mode " },
+ { 0x56, 0x01, 0x00, M_EN, 0 },
+
+ /* DRAMC - DRAM Control Register */
+ { 0x00, 0x00, 0x00, M_TR, "\n\tHole: " },
+ { 0x57, 0xc0, 0x00, M_EQ, "None" },
+ { 0x57, 0xc0, 0x40, M_EQ, "512KB - 640KB" },
+ { 0x00, 0x00, 0x00, M_TR, ", EDO Detect mode " },
+ { 0x57, 0x04, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tDRAM Refrest Rate " },
+ { 0x57, 0x07, 0x00, M_EQ, "Disabled" },
+ { 0x57, 0x07, 0x01, M_EQ, "50Mhz" },
+ { 0x57, 0x07, 0x02, M_EQ, "60Mhz" },
+ { 0x57, 0x07, 0x03, M_EQ, "66Mhz" },
+
+ /* DRAMT -- DRAM Timing Register */
+ { 0x00, 0x00, 0x00, M_TR, "\n\tTurbo Read Leadoff " },
+ { 0x58, 0x80, 0x00, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tDRAM Read Burst Timing: " },
+ { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
+ { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
+ { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tDRAM Write Burst Timing: " },
+ { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
+ { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
+ { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tFast RAS to CAS Delay: " },
+ { 0x58, 0x04, 0x00, M_EQ, "3" },
+ { 0x58, 0x04, 0x04, M_EQ, "2" },
+ { 0x00, 0x00, 0x00, M_TR, " clocks,\n\tDRAM leadoff Timing: " },
+ { 0x58, 0x03, 0x00, M_EQ, "Read 7, Write 6, Precharge 3, Refresh 4" },
+ { 0x58, 0x03, 0x01, M_EQ, "Read 6, Write 5, Precharge 3, Refresh 4" },
+ { 0x58, 0x03, 0x02, M_EQ, "Read 7, Write 6, Precharge 4, Refresh 5" },
+ { 0x58, 0x03, 0x03, M_EQ, "Read 6, Write 5, Precharge 4, Refresh 5" },
+ { 0x00, 0x00, 0x00, M_TR, "\n" },
+
+ /* end marker */
+ { 0 }
+
+ };
+
static const struct condmsg conf82371fb[] =
{
/* IORT -- ISA I/O Recovery Timer Register */
***************
*** 616,621 ****
--- 708,717 ----
case 0x122e8086:
writeconfig (config_id, conf82371fb);
break;
+ case 0x12508086:
+ writeconfig (config_id, conf82439hx);
+ break;
+
#if 0
case 0x00011011: /* DEC 21050 */
case 0x00221014: /* IBM xxx */
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