From owner-cvs-src@FreeBSD.ORG Mon May 3 23:58:11 2004 Return-Path: Delivered-To: cvs-src@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id A011416A4CE; Mon, 3 May 2004 23:58:11 -0700 (PDT) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 8E44543D49; Mon, 3 May 2004 23:58:11 -0700 (PDT) (envelope-from marcel@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.10/8.12.10) with ESMTP id i446wBGe073712; Mon, 3 May 2004 23:58:11 -0700 (PDT) (envelope-from marcel@repoman.freebsd.org) Received: (from marcel@localhost) by repoman.freebsd.org (8.12.10/8.12.10/Submit) id i446wBEh073711; Mon, 3 May 2004 23:58:11 -0700 (PDT) (envelope-from marcel) Message-Id: <200405040658.i446wBEh073711@repoman.freebsd.org> From: Marcel Moolenaar Date: Mon, 3 May 2004 23:58:11 -0700 (PDT) To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/dev/uart uart_dev_z8530.c X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 May 2004 06:58:11 -0000 marcel 2004/05/03 23:58:10 PDT FreeBSD src repository Modified files: sys/dev/uart uart_dev_z8530.c Log: Fix hangs caused by z8530_bus_ipend() returning UART_IPEND_TXIDLE not as a pending interrupt status, but as a matter of status quo. Consequently, when there's no data to be transmitted the condition is not cleared and uart_intr() is stuck in an infinite loop trying to clear the UART_IPEND_TXIDLE status. The z8530_bus_ipend() function is changed to return idle only once after having sent any data. The root cause for this problem is that we cannot use the interrupt status bits of the SCC itself. The register that holds the interrupt status can only be accessed by channel A and holds the status for both channels. Using the interrupt status register would complicate the driver because we need to synchronize access to the SCC between the channels. Elementary testing: marius Revision Changes Path 1.7 +7 -1 src/sys/dev/uart/uart_dev_z8530.c