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From: Dimitry Andric <dim@FreeBSD.org>
Date: Mon, 14 Nov 2016 18:57:22 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r308648 - stable/11/contrib/llvm/lib/Target/AArch64
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Author: dim
Date: Mon Nov 14 18:57:21 2016
New Revision: 308648
URL: https://svnweb.freebsd.org/changeset/base/308648

Log:
  MFC r308559:
  
  Pull in r263169 from upstream llvm trunk (by Tim Northover):
  
    AArch64: only try to use scaled fcvt ops on legal vector types.
  
    Before we ended up calling getSimpleVectorType on a <3 x float>, which
    asserted.
  
  This fixes an assertion when building the print/ghostscript9-agpl-base
  port for AArch64.
  
  PR:		213865

Modified:
  stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Directory Properties:
  stable/11/   (props changed)

Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp	Mon Nov 14 18:54:31 2016	(r308647)
+++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp	Mon Nov 14 18:57:21 2016	(r308648)
@@ -7581,7 +7581,8 @@ static SDValue performFpToIntCombine(SDN
     return SDValue();
 
   SDValue Op = N->getOperand(0);
-  if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
+  if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
+      Op.getOpcode() != ISD::FMUL)
     return SDValue();
 
   SDValue ConstVec = Op->getOperand(1);