Date: Wed, 30 Aug 2006 19:24:35 +0900 From: Ganbold <ganbold@micom.mng.net> To: Gleb Smirnoff <glebius@FreeBSD.org> Cc: Pyun YongHyeon <pyunyh@gmail.com>, freebsd-stable@FreeBSD.org, oleg@FreeBSD.org Subject: Re: panic: invalid ife->ifm_data (0xa) in mii_phy_setmedia Message-ID: <44F56763.9040409@micom.mng.net> In-Reply-To: <20060830085331.GT76666@cell.sick.ru> References: <44F4F1DE.2030907@micom.mng.net> <20060830023537.GA47208@cdnetworks.co.kr> <44F504A8.8070503@micom.mng.net> <20060830073025.GB47208@cdnetworks.co.kr> <20060830075012.GP76666@cell.sick.ru> <44F54B9F.8010508@micom.mng.net> <20060830085331.GT76666@cell.sick.ru>
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Gleb Smirnoff wrote:
> On Wed, Aug 30, 2006 at 05:26:07PM +0900, Ganbold wrote:
> G> Gleb, Pyun,
> G>
> G> I'm a kind of bit confused here whose patch to choose.
> G> Can you guys enlighten me in this regard?
>
> Can you please merge them? You should take all the stuff that
> prepares the dma_rw_ctl variable from my patch, and all the other
> stuff from Pyun's patch.
>
>
Ok, here it is. Let me know if I did something wrong.
It also includes delphij@'s patch. Pyun's brgphy(4) patch is included too.
Ganbold
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Content-Type: text/x-patch;
name="if_bge_combined.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="if_bge_combined.patch"
--- if_bge.c Thu Aug 10 20:02:14 2006
+++ /home/tsgan/bge/new/if_bge.c Wed Aug 30 18:41:39 2006
@@ -1005,36 +1005,48 @@
BGE_MEMWIN_WRITE(sc, i, 0);
/* Set up the PCI DMA control register. */
+ dma_rw_ctl = BGE_PCIDMARWCTL_READ_CMD | BGE_PCIDMARWCTL_WRITE_CMD;
+
+ /* Bits 23, 22. */
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5701 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5714)
+ dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE |
+ BGE_PCIDMARWCTL_USE_MRM;
+
+ /* DMA watermarks: bits 21 - 19, 18 - 16. */
if (sc->bge_pcie) {
- /* PCI Express bus */
- dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
- (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
- (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
+ /*
+ * DMA read watermark not used on PCI-E.
+ * DMA write watermark set to 128 bytes.
+ */
+ dma_rw_ctl |= (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
} else if (sc->bge_pcix) {
- /* PCI-X bus */
- if (BGE_IS_5714_FAMILY(sc)) {
- dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
- dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
- /* XXX magic values, Broadcom-supplied Linux driver */
- if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
- dma_rw_ctl |= (1 << 20) | (1 << 18) |
- BGE_PCIDMARWCTL_ONEDMA_ATONCE;
- else
- dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
-
- } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
+ switch (sc->bge_asicrev) {
+ case BGE_ASICREV_BCM5780:
+ /* XXX: Linux driver magic values. */
+ dma_rw_ctl |= (1 << 20) | (1 << 18) |
+ BGE_PCIDMARWCTL_ONEDMA_ATONCE;
+ break;
+ case BGE_ASICREV_BCM5714:
+ case BGE_ASICREV_BCM5714_A0:
+ /* XXX: Linux driver magic values. */
+ dma_rw_ctl |= (1 << 20) | (1 << 18) |
+ BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
+ break;
+ case BGE_ASICREV_BCM5704:
/*
* The 5704 uses a different encoding of read/write
- * watermarks.
+ * watermarks: 384 bytes for write and 1536 for read.
*/
- dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
- (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
- (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
- else
- dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
- (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
- (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
- (0x0F);
+ dma_rw_ctl |= (7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
+ (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
+ break;
+ default:
+ /* All other chips: 384 for write and read. */
+ dma_rw_ctl |= (3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
+ (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
+ }
/*
* 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
@@ -1047,18 +1059,20 @@
tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
if (tmp == 0x6 || tmp == 0x7)
dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
+
+ /* Set bit 23 to enable PCIX hw bug fix. */
+ dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
}
} else
- /* Conventional PCI bus */
- dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
- (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
- (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
- (0x0F);
-
- if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
- sc->bge_asicrev == BGE_ASICREV_BCM5705)
- dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
+ /* Conventional PCI bus: 1024 bytes for read and write. */
+ dma_rw_ctl |= (7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
+ (7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
+
+ /* Set minimum DMA only for 5700 and 5701. */
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5701)
+ dma_rw_ctl |= 0xf;
+
pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
/*
@@ -1148,22 +1162,20 @@
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
/* Enable buffer manager */
- if (!(BGE_IS_5705_OR_BEYOND(sc))) {
- CSR_WRITE_4(sc, BGE_BMAN_MODE,
- BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
+ CSR_WRITE_4(sc, BGE_BMAN_MODE,
+ BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
- /* Poll for buffer manager start indication */
- for (i = 0; i < BGE_TIMEOUT; i++) {
- if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
- break;
- DELAY(10);
- }
+ /* Poll for buffer manager start indication */
+ for (i = 0; i < BGE_TIMEOUT; i++) {
+ if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
+ break;
+ DELAY(10);
+ }
- if (i == BGE_TIMEOUT) {
- device_printf(sc->bge_dev,
- "buffer manager failed to start\n");
- return (ENXIO);
- }
+ if (i == BGE_TIMEOUT) {
+ device_printf(sc->bge_dev,
+ "buffer manager failed to start\n");
+ return (ENXIO);
}
/* Enable flow-through queues */
@@ -2309,6 +2321,13 @@
pci_write_config(dev, BGE_PCI_MISC_CTL,
BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
+
+ /* XXX: Broadcom Linux driver. */
+ if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
+ sc->bge_asicrev == BGE_ASICREV_BCM5787) {
+ CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
+ }
reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
--------------010704030302090107030908
Content-Type: text/x-patch;
name="if_bgereg_combined.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="if_bgereg_combined.patch"
--- if_bgereg.h Thu Aug 10 20:02:14 2006
+++ /home/tsgan/bge/new/if_bgereg.h Wed Aug 30 18:15:08 2006
@@ -196,6 +196,15 @@
#define BGE_PCI_ISR_MBX_HI 0xB0
#define BGE_PCI_ISR_MBX_LO 0xB4
+/* XXX:
+ * Used in PCI-Express code for 575x chips.
+ * Should be replaced with checking for a PCI config-space
+ * capability for PCI-Express, and PCI-Express standard
+ * offsets into that capability block.
+ */
+#define BGE_PCI_CONF_DEV_CTRL 0xD8
+#define BGE_PCI_CONF_DEV_STUS 0xDA
+
/* PCI Misc. Host control register */
#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
@@ -290,20 +299,29 @@
#define BGE_CHIPREV_5701_AX 0x00
/* PCI DMA Read/Write Control register */
+#define BGE_PCIDMARWCTL_WRITE_CMD 0x70000000
+#define BGE_PCIDMARWCTL_READ_CMD 0x06000000
+
#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000
+#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
+#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000
#define BGE_PCIDMARWCTL_RD_WAT 0x00070000
-# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
+#define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
#define BGE_PCIDMARWCTL_WR_WAT 0x00380000
-# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
+#define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
#define BGE_PCIDMARWCTL_USE_MRM 0x00400000
#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
-# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
+#define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
-# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
+#define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
+
+/* PCI DMA Read/Write Control register, alternate usage for PCI-Express */
+#define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128 0x00180000
+#define BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256 0x00380000
#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
@@ -1656,6 +1674,7 @@
#define BGE_EE_CTL 0x6840
#define BGE_MDI_CTL 0x6844
#define BGE_EE_DELAY 0x6848
+#define BGE_FASTBOOT_PC 0x6894
/* Mode control register */
#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
@@ -2074,9 +2093,6 @@
#define BGE_MEDIA_UNSPEC 0x00000000
#define BGE_MEDIA_COPPER 0x00000010
#define BGE_MEDIA_FIBER 0x00000020
-
-#define BGE_PCI_READ_CMD 0x06000000
-#define BGE_PCI_WRITE_CMD 0x70000000
#define BGE_TICKS_PER_SEC 1000000
--------------010704030302090107030908
Content-Type: text/x-patch;
name="brgphy.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="brgphy.patch"
Index: miidevs
===================================================================
RCS file: /home/ncvs/src/sys/dev/mii/miidevs,v
retrieving revision 1.30.2.3
diff -u -r1.30.2.3 miidevs
--- miidevs 8 Aug 2006 07:51:21 -0000 1.30.2.3
+++ miidevs 30 Aug 2006 02:28:07 -0000
@@ -118,6 +118,7 @@
model xxBROADCOM BCM5400 0x0004 Broadcom 1000baseTX PHY
model xxBROADCOM BCM5401 0x0005 BCM5401 10/100/1000baseTX PHY
model xxBROADCOM BCM5411 0x0007 BCM5411 10/100/1000baseTX PHY
+model xxBROADCOM BCM5752 0x0010 BCM5752 10/100/1000baseTX PHY
model xxBROADCOM BCM5701 0x0011 BCM5701 10/100/1000baseTX PHY
model xxBROADCOM BCM5703 0x0016 BCM5703 10/100/1000baseTX PHY
model xxBROADCOM BCM5704 0x0019 BCM5704 10/100/1000baseTX PHY
Index: brgphy.c
===================================================================
RCS file: /home/ncvs/src/sys/dev/mii/brgphy.c,v
retrieving revision 1.34.2.6
diff -u -r1.34.2.6 brgphy.c
--- brgphy.c 8 Aug 2006 04:37:18 -0000 1.34.2.6
+++ brgphy.c 30 Aug 2006 02:28:07 -0000
@@ -126,6 +126,12 @@
}
if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
+ MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5752) {
+ device_set_desc(dev, MII_STR_xxBROADCOM_BCM5752);
+ return(BUS_PROBE_DEFAULT);
+ }
+
+ if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM &&
MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) {
device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701);
return(BUS_PROBE_DEFAULT);
@@ -665,6 +671,7 @@
bcm5704_load_dspcode(sc);
break;
case MII_MODEL_xxBROADCOM_BCM5750:
+ case MII_MODEL_xxBROADCOM_BCM5752:
case MII_MODEL_xxBROADCOM_BCM5714:
case MII_MODEL_xxBROADCOM_BCM5780:
case MII_MODEL_xxBROADCOM_BCM5706C:
--------------010704030302090107030908--
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