From owner-freebsd-drivers@freebsd.org Mon Aug 20 06:49:34 2018 Return-Path: Delivered-To: freebsd-drivers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 0F3961086445; Mon, 20 Aug 2018 06:49:34 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from kabab.cs.huji.ac.il (kabab.cs.huji.ac.il [132.65.116.210]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 11A347E40D; Mon, 20 Aug 2018 06:49:32 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from bach.cs.huji.ac.il ([132.65.80.20]) by kabab.cs.huji.ac.il with esmtp id 1fre0D-000FYp-EW; Mon, 20 Aug 2018 09:49:25 +0300 From: Daniel Braniss Message-Id: Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Date: Mon, 20 Aug 2018 09:49:25 +0300 In-Reply-To: <1534702861.27158.36.camel@freebsd.org> Cc: Rajesh Kumar , freebsd-hackers@freebsd.org, freebsd-drivers@freebsd.org To: Ian Lepore References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> X-Mailer: Apple Mail (2.3445.9.1) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-drivers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Writing device drivers for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 06:49:35 -0000 > On 19 Aug 2018, at 21:21, Ian Lepore wrote: >=20 > On Sun, 2018-08-19 at 19:23 +0530, Rajesh Kumar wrote: >> Hi Ian, >>=20 >> Basically, I want to set the I2C clock frequency for Designware IP in = our >> board to 150Mhz. So, I was looking for the way in FreeBSD. >>=20 >> So, Is this the frequency which is configured through the clock = high/low >> registers? I see the those register are coded to 100 and 125 = currently, I >> am not sure how that value is arrived. If it needs to be configured = for >> 150Mhz, how to derive the appropriate values? I looked at the = DW_apb_i2c >> databook section 3.11 to understand about it. I am still unclear. I = see a >> comment saying "Program based on 25000 Hz clock". In my case, should = they >> be programmed based on 150Mhz clock? >=20 > Rajesh, >=20 > Please bottom-post when replying on freebsd mailing lists, mixed top- > and bottom-posting is too confusing. >=20 > What exactly do you mean when you say "the i2c clock frequency"? >=20 > The datasheet appears to use a term like that to refer to the internal > clock used to drive the IP block in the chip. That base clock is then > divided down to create the i2c bus frequency on the I2C_SCL line. >=20 > The IG4_REG_SS_SCL_HCNT and IG4_REG_SS_SCL_LCNT registers are the > duration in base clock ticks that the SCL line is held high and low = for > standard speed. The registers with FS in the name are for high speed > mode. >=20 > The comment block and the values our driver programs into those > registers appear to be wildly wrong. There is no way a base clock > running at 25KHz can be divided down to create i2c bus speeds of = 100KHz > and 400KHz for standard and fast modes. If the base clock really is > 25KHz then the driver currently sets the i2c bus to run at 111Hz. >=20 > The hardware default values for the HCNT/LCNT registers, as given in > the datasheet referenced by the driver [1], would be consistant with = an > internal base clock speed of 1GHz. The fact that the header file > defines a IG4_REG_CLK_PARMS register, but the datasheet doesn't = mention > it, makes me think that on some versions of the hardware the speed is > fixed and the driver has to know what that is based on the version, or > vendor, or something. Other versions of the hardware may have > information about the base clock speed in that IG4_REG_CLK_PARMS > register. >=20 > What we need is for someone who has this hardware to put an > oscilliscope on the SCL line and get us some real-world truth. >=20 > [1] = http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family= -mobile-i-o-datasheet.html?wapkw=3Ddatasheets+4th+generation = >=20 > -- Ian hi, I have similar issues with the allwinner/twsi but I do have a Saleae = Logic and here is a nice picture: danny