Date: Wed, 29 Apr 2015 14:05:42 -0600 From: Warner Losh <imp@bsdimp.com> To: Jason Harmening <jason.harmening@gmail.com> Cc: Konstantin Belousov <kostikbel@gmail.com>, Svatopluk Kraus <onwahe@gmail.com>, John Baldwin <jhb@freebsd.org>, Adrian Chadd <adrian@freebsd.org>, freebsd-arch <freebsd-arch@freebsd.org> Subject: Re: bus_dmamap_sync() for bounced client buffers from user address space Message-ID: <9807ECB0-5218-42D1-9BD9-94F6BB5C69C8@bsdimp.com> In-Reply-To: <CAM=8qanPHbCwUeu0-zi-ccY4WprHaOGzCm44PwNSgb==nwgGGw@mail.gmail.com> References: <CAFHCsPXMjge84AR2cR8KXMXWP4kH2YvuV_uqtPKUvn5C3ygknw@mail.gmail.com> <38574E63-2D74-4ECB-8D68-09AC76DFB30C@bsdimp.com> <CAJ-VmomqGkEFVauya%2BrmPGcD_-=Z-mmg1RSDf1D2bT_DfwPBGA@mail.gmail.com> <1761247.Bq816CMB8v@ralph.baldwin.cx> <CAFHCsPX9rgmCAPABct84a000NuBPQm5sprOAQr9BTT6Ev6KZcQ@mail.gmail.com> <20150429132017.GM2390@kib.kiev.ua> <CAFHCsPWjEFBF%2B-7SR7EJ3UHP6oAAa9xjbu0CbRaQvd_-6gKuAQ@mail.gmail.com> <20150429165432.GN2390@kib.kiev.ua> <CAM=8qakzkKX8TZNYE33H=JqL_r5z%2BAU9fyp5%2B7Z0mixmF5t63w@mail.gmail.com> <20150429185019.GO2390@kib.kiev.ua> <CAM=8qanPHbCwUeu0-zi-ccY4WprHaOGzCm44PwNSgb==nwgGGw@mail.gmail.com>
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--Apple-Mail=_BE24FC7E-A878-4059-963E-1A19E29BB82A Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=us-ascii > On Apr 29, 2015, at 1:17 PM, Jason Harmening = <jason.harmening@gmail.com> wrote: >=20 >=20 >=20 >=20 > Yes, that needs to be done regardless of how the pages are wired. The = particular problem here is that some caches on arm and mips are = virtually-indexed (usually virtually-indexed, physically-tagged (VIPT)). = That means the flush/invalidate instructions need virtual addresses, so = figuring out the correct UVA to use for those could be a challenge. As = I understand it, VIPT caches usually do have some hardware logic for = finding all the cachelines that correspond to a physical address, so = they can handle multiple VA mappings of the same PA. But it is unclear = to me how cross-processor cache maintenance is supposed to work with = VIPT caches on SMP systems. >=20 > If the caches were physically-indexed, then I don't think there would = be an issue. You'd just pass the PA to the flush/invalidate = instruction, and presumably a sane SMP implementation would propagate = that to other cores via IPI. I know on MIPS you cannot have more than one mapping to a page you are = doing DMA to/from ever. Warner --Apple-Mail=_BE24FC7E-A878-4059-963E-1A19E29BB82A Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc Content-Type: application/pgp-signature; name=signature.asc Content-Description: Message signed with OpenPGP using GPGMail -----BEGIN PGP SIGNATURE----- Comment: GPGTools - https://gpgtools.org iQIcBAEBCgAGBQJVQTmXAAoJEGwc0Sh9sBEAk9UP/0EXZ/oWomX5qr9eSByKloVy m7MthNOYTTFnHhJlrtOSspQ/OZdsBoK1lzgNhcvjQRtXzDyelK1fDP5iYla1w5Lt XAwcL8yIjUBUm1SmHdY9O/rBLrMaeg03sEUJzaLGtF1V5dRrvHr/UsQpegcEy2Kw +4m5aSAZmr9MPIJ+r/1ztilvZv9k26pDQ1UdUvCpq7/c28A9JWdhbGSwuNpFzOI/ WSy+7fxBH4WbeC9ikRkkoIqmAEO2EAaecMnRAHbTzoPhKnQahtzXC14BSUzpNKL2 HSkXZK0INc12VEocr/rovNP4iTRe4HrcN4nPHIeyKNjJdm2Pu8bo39yU4FWBzTkt efnTd9jGAy3Sqy+YJFZSKkRxYjMDSP6qmp+bD/8vRUf7z5AiB20zUxPQ0fCmXdLX F5MTlAjRdQ/I9+HHEOIqk1ZkPAQJP5Zz6KzTm7WLBBIdSC7sqewOsw5iSXufssCl 80pg/er17pyCm4PsmR+i4fwi5UtgGkNt0gUcScWDqHcItFX9tHTrSb/OpFEa5WvW pcordomq6pOQ3f23lG/R964yLu3hlCf9Jrhznom9/FwzMoS1cKsNQVGUS0Pwa6aa M+egJHSmhz8weoGry4ygBrIq8jLOHB+xnobLGHPqiPk/q5IGwI5o1m0ODquO2pD8 g2ckIm17cRCNmvLJzhAu =axbV -----END PGP SIGNATURE----- --Apple-Mail=_BE24FC7E-A878-4059-963E-1A19E29BB82A--
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