Date: Wed, 2 Jan 2013 09:32:26 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 219933 for review Message-ID: <201301020932.r029WQEm074131@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@219933?ac=10 Change 219933 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/02 09:32:16 Implement an FDT PIC decode routine to use when no PIC has been configured, which assumes a cascade back to the nexus bus (e.g., the on-board CP0 interrupt management parts on the MIPS). If the soc bus in a MIPS DTS file is declared as "mips4k,cp0"-compatible, then this will be enabled. This is sufficient to allow IRQs to be configured on BERI. Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/dev/fdt/fdt_mips.c#2 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/dev/fdt/fdt_mips.c#2 (text+ko) ==== @@ -49,8 +49,26 @@ { NULL, NULL } }; +/* + * For PIC-free boards, provide a PIC decoder to be used with mips4k CP0 + * interrupt control directly. + */ +static int +fdt_pic_decode_mips4k_cp0(phandle_t node, pcell_t *intr, int *interrupt, + int *trig, int *pol) +{ + + if (!fdt_is_compatible(node, "mips4k,cp0")) + return (ENXIO); + + *interrupt = fdt32_to_cpu(intr[0]); + *trig = INTR_TRIGGER_CONFORM; + *pol = INTR_POLARITY_CONFORM; + + return (0); +} + fdt_pic_decode_t fdt_pic_table[] = { - NULL, - NULL, + &fdt_pic_decode_mips4k_cp0, NULL };
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