Date: Fri, 26 Mar 2010 15:52:32 +0000 (UTC) From: Nathan Whitehorn <nwhitehorn@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r205700 - in projects/ppc64/sys/powerpc: aim booke include powerpc Message-ID: <201003261552.o2QFqWWt090612@svn.freebsd.org>
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Author: nwhitehorn Date: Fri Mar 26 15:52:32 2010 New Revision: 205700 URL: http://svn.freebsd.org/changeset/base/205700 Log: Take some extra care with MSR values. First, define them to longs so that setting SRR1 &= ~PSL_SE does not accidentally unset 64-bit mode. Second, make sure that, in the 64-bit case, PSL_HV is explicitly preserved when returning from interrupts. Modified: projects/ppc64/sys/powerpc/aim/locore32.S projects/ppc64/sys/powerpc/aim/locore64.S projects/ppc64/sys/powerpc/aim/swtch32.S projects/ppc64/sys/powerpc/aim/swtch64.S projects/ppc64/sys/powerpc/booke/locore.S projects/ppc64/sys/powerpc/booke/swtch.S projects/ppc64/sys/powerpc/include/psl.h projects/ppc64/sys/powerpc/powerpc/exec_machdep.c projects/ppc64/sys/powerpc/powerpc/genassym.c Modified: projects/ppc64/sys/powerpc/aim/locore32.S ============================================================================== --- projects/ppc64/sys/powerpc/aim/locore32.S Fri Mar 26 15:50:01 2010 (r205699) +++ projects/ppc64/sys/powerpc/aim/locore32.S Fri Mar 26 15:52:32 2010 (r205700) @@ -63,7 +63,6 @@ #include <machine/trap.h> #include <machine/param.h> #include <machine/spr.h> -#include <machine/psl.h> #include <machine/asm.h> /* Locate the per-CPU data structure */ Modified: projects/ppc64/sys/powerpc/aim/locore64.S ============================================================================== --- projects/ppc64/sys/powerpc/aim/locore64.S Fri Mar 26 15:50:01 2010 (r205699) +++ projects/ppc64/sys/powerpc/aim/locore64.S Fri Mar 26 15:52:32 2010 (r205700) @@ -63,7 +63,6 @@ #include <machine/trap.h> #include <machine/param.h> #include <machine/spr.h> -#include <machine/psl.h> #include <machine/asm.h> /* Locate the per-CPU data structure */ Modified: projects/ppc64/sys/powerpc/aim/swtch32.S ============================================================================== --- projects/ppc64/sys/powerpc/aim/swtch32.S Fri Mar 26 15:50:01 2010 (r205699) +++ projects/ppc64/sys/powerpc/aim/swtch32.S Fri Mar 26 15:52:32 2010 (r205700) @@ -63,7 +63,6 @@ #include <machine/trap.h> #include <machine/param.h> -#include <machine/psl.h> #include <machine/asm.h> /* Modified: projects/ppc64/sys/powerpc/aim/swtch64.S ============================================================================== --- projects/ppc64/sys/powerpc/aim/swtch64.S Fri Mar 26 15:50:01 2010 (r205699) +++ projects/ppc64/sys/powerpc/aim/swtch64.S Fri Mar 26 15:52:32 2010 (r205700) @@ -63,7 +63,6 @@ #include <machine/trap.h> #include <machine/param.h> -#include <machine/psl.h> #include <machine/asm.h> /* Modified: projects/ppc64/sys/powerpc/booke/locore.S ============================================================================== --- projects/ppc64/sys/powerpc/booke/locore.S Fri Mar 26 15:50:01 2010 (r205699) +++ projects/ppc64/sys/powerpc/booke/locore.S Fri Mar 26 15:52:32 2010 (r205700) @@ -34,7 +34,6 @@ #include <machine/hid.h> #include <machine/param.h> #include <machine/spr.h> -#include <machine/psl.h> #include <machine/pte.h> #include <machine/trap.h> #include <machine/vmparam.h> Modified: projects/ppc64/sys/powerpc/booke/swtch.S ============================================================================== --- projects/ppc64/sys/powerpc/booke/swtch.S Fri Mar 26 15:50:01 2010 (r205699) +++ projects/ppc64/sys/powerpc/booke/swtch.S Fri Mar 26 15:52:32 2010 (r205700) @@ -64,7 +64,6 @@ #include <machine/trap.h> #include <machine/param.h> -#include <machine/psl.h> #include <machine/asm.h> #include <machine/spr.h> Modified: projects/ppc64/sys/powerpc/include/psl.h ============================================================================== --- projects/ppc64/sys/powerpc/include/psl.h Fri Mar 26 15:50:01 2010 (r205699) +++ projects/ppc64/sys/powerpc/include/psl.h Fri Mar 26 15:52:32 2010 (r205700) @@ -44,23 +44,23 @@ * FP, FE0, FE1 - reserved, always cleared, setting has no effect. * */ -#define PSL_UCLE 0x04000000 /* User mode cache lock enable */ -#define PSL_SPE 0x02000000 /* SPE enable */ -#define PSL_WE 0x00040000 /* Wait state enable */ -#define PSL_CE 0x00020000 /* Critical interrupt enable */ -#define PSL_EE 0x00008000 /* External interrupt enable */ -#define PSL_PR 0x00004000 /* User mode */ -#define PSL_FP 0x00002000 /* Floating point available */ -#define PSL_ME 0x00001000 /* Machine check interrupt enable */ -#define PSL_FE0 0x00000800 /* Floating point exception mode 0 */ -#define PSL_UBLE 0x00000400 /* BTB lock enable */ -#define PSL_DE 0x00000200 /* Debug interrupt enable */ -#define PSL_FE1 0x00000100 /* Floating point exception mode 1 */ -#define PSL_IS 0x00000020 /* Instruction address space */ -#define PSL_DS 0x00000010 /* Data address space */ -#define PSL_PMM 0x00000004 /* Performance monitor mark */ +#define PSL_UCLE 0x04000000UL /* User mode cache lock enable */ +#define PSL_SPE 0x02000000UL /* SPE enable */ +#define PSL_WE 0x00040000UL /* Wait state enable */ +#define PSL_CE 0x00020000UL /* Critical interrupt enable */ +#define PSL_EE 0x00008000UL /* External interrupt enable */ +#define PSL_PR 0x00004000UL /* User mode */ +#define PSL_FP 0x00002000UL /* Floating point available */ +#define PSL_ME 0x00001000UL /* Machine check interrupt enable */ +#define PSL_FE0 0x00000800UL /* Floating point exception mode 0 */ +#define PSL_UBLE 0x00000400UL /* BTB lock enable */ +#define PSL_DE 0x00000200UL /* Debug interrupt enable */ +#define PSL_FE1 0x00000100UL /* Floating point exception mode 1 */ +#define PSL_IS 0x00000020UL /* Instruction address space */ +#define PSL_DS 0x00000010UL /* Data address space */ +#define PSL_PMM 0x00000004UL /* Performance monitor mark */ -#define PSL_FE_DFLT 0x00000000 /* default == none */ +#define PSL_FE_DFLT 0x00000000UL /* default == none */ /* Initial kernel MSR, use IS=1 ad DS=1. */ #define PSL_KERNSET_INIT (PSL_IS | PSL_DS) @@ -77,27 +77,30 @@ * * [*] Little-endian mode on the 601 is implemented in the HID0 register. */ -#define PSL_VEC 0x02000000 /* AltiVec vector unit available */ -#define PSL_POW 0x00040000 /* power management */ -#define PSL_ILE 0x00010000 /* interrupt endian mode (1 == le) */ -#define PSL_EE 0x00008000 /* external interrupt enable */ -#define PSL_PR 0x00004000 /* privilege mode (1 == user) */ -#define PSL_FP 0x00002000 /* floating point enable */ -#define PSL_ME 0x00001000 /* machine check enable */ -#define PSL_FE0 0x00000800 /* floating point interrupt mode 0 */ -#define PSL_SE 0x00000400 /* single-step trace enable */ -#define PSL_BE 0x00000200 /* branch trace enable */ -#define PSL_FE1 0x00000100 /* floating point interrupt mode 1 */ -#define PSL_IP 0x00000040 /* interrupt prefix */ -#define PSL_IR 0x00000020 /* instruction address relocation */ -#define PSL_DR 0x00000010 /* data address relocation */ -#define PSL_RI 0x00000002 /* recoverable interrupt */ -#define PSL_LE 0x00000001 /* endian mode (1 == le) */ #ifdef __powerpc64__ -#define PSL_SF (0x1UL << 63) +#define PSL_SF 0x1000000000000000UL /* 64-bit addressing */ +#define PSL_HV 0x3000000000000000UL /* hyper-privileged mode */ #endif +#define PSL_VEC 0x02000000UL /* AltiVec vector unit available */ +#define PSL_POW 0x00040000UL /* power management */ +#define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */ +#define PSL_EE 0x00008000UL /* external interrupt enable */ +#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */ +#define PSL_FP 0x00002000UL /* floating point enable */ +#define PSL_ME 0x00001000UL /* machine check enable */ +#define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */ +#define PSL_SE 0x00000400UL /* single-step trace enable */ +#define PSL_BE 0x00000200UL /* branch trace enable */ +#define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */ +#define PSL_IP 0x00000040UL /* interrupt prefix */ +#define PSL_IR 0x00000020UL /* instruction address relocation */ +#define PSL_DR 0x00000010UL /* data address relocation */ +#define PSL_PMM 0x00000004UL /* performance monitor mark */ +#define PSL_RI 0x00000002UL /* recoverable interrupt */ +#define PSL_LE 0x00000001UL /* endian mode (1 == le) */ + #define PSL_601_MASK ~(PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE) /* Modified: projects/ppc64/sys/powerpc/powerpc/exec_machdep.c ============================================================================== --- projects/ppc64/sys/powerpc/powerpc/exec_machdep.c Fri Mar 26 15:50:01 2010 (r205699) +++ projects/ppc64/sys/powerpc/powerpc/exec_machdep.c Fri Mar 26 15:52:32 2010 (r205700) @@ -552,6 +552,8 @@ exec_setregs(struct thread *td, struct i tf->fixreg[2] = entry_desc[1] + imgp->reloc_base; tf->fixreg[11] = entry_desc[2] + imgp->reloc_base; tf->srr1 = PSL_SF | PSL_USERSET | PSL_FE_DFLT; + if (mfmsr() & PSL_HV) + tf->srr1 |= PSL_HV; #else tf->srr0 = imgp->entry_addr; tf->srr1 = PSL_USERSET | PSL_FE_DFLT; @@ -584,6 +586,8 @@ ppc32_setregs(struct thread *td, struct tf->srr0 = imgp->entry_addr; tf->srr1 = PSL_MBO | PSL_USERSET | PSL_FE_DFLT; tf->srr1 &= ~PSL_SF; + if (mfmsr() & PSL_HV) + tf->srr1 |= PSL_HV; td->td_pcb->pcb_flags = 0; } #endif @@ -1033,8 +1037,15 @@ cpu_set_upcall_kse(struct thread *td, vo tf->fixreg[2] = entry_desc[1]; tf->fixreg[11] = entry_desc[2]; tf->srr1 = PSL_SF | PSL_MBO | PSL_USERSET | PSL_FE_DFLT; + if (mfmsr() & PSL_HV) + tf->srr1 |= PSL_HV; #endif } + + #ifdef __powerpc64__ + if (mfmsr() & PSL_HV) + tf->srr1 |= PSL_HV; + #endif td->td_pcb->pcb_flags = 0; td->td_retval[0] = (register_t)entry; Modified: projects/ppc64/sys/powerpc/powerpc/genassym.c ============================================================================== --- projects/ppc64/sys/powerpc/powerpc/genassym.c Fri Mar 26 15:50:01 2010 (r205699) +++ projects/ppc64/sys/powerpc/powerpc/genassym.c Fri Mar 26 15:52:32 2010 (r205700) @@ -53,6 +53,7 @@ #include <machine/pcb.h> #include <machine/pmap.h> +#include <machine/psl.h> #include <machine/sigframe.h> ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread)); @@ -209,3 +210,50 @@ ASSYM(SF_UC, offsetof(struct sigframe, s ASSYM(KERNBASE, KERNBASE); ASSYM(MAXCOMLEN, MAXCOMLEN); + +#ifdef E500 +ASSYM(PSL_UCLE, PSL_UCLE); +ASSYM(PSL_SPE, PSL_SPE); +ASSYM(PSL_WE, PSL_WE); +ASSYM(PSL_CE, PSL_CE); +ASSYM(PSL_UBLE, PSL_UBLE); +ASSYM(PSL_DS, PSL_DS); +ASSYM(PSL_IS, PSL_IS); +ASSYM(PSL_DE, PSL_DE); + +ASSYM(PSL_KERNSET_INIT, PSL_KERNSET_INIT); +#else /* AIM */ +#ifdef __powerpc64__ +ASSYM(PSL_SF, PSL_SF); +ASSYM(PSL_HV, PSL_HV); +#endif +ASSYM(PSL_VEC, PSL_VEC); +ASSYM(PSL_POW, PSL_POW); +ASSYM(PSL_ILE, PSL_ILE); +ASSYM(PSL_BE, PSL_BE); +ASSYM(PSL_LE, PSL_LE); +ASSYM(PSL_SE, PSL_SE); +ASSYM(PSL_RI, PSL_RI); +ASSYM(PSL_DR, PSL_DR); +ASSYM(PSL_IP, PSL_IP); +ASSYM(PSL_IR, PSL_IR); + +ASSYM(PSL_FE_DIS, PSL_FE_DIS); +ASSYM(PSL_FE_NONREC, PSL_FE_NONREC); +ASSYM(PSL_FE_PREC, PSL_FE_PREC); +ASSYM(PSL_FE_REC, PSL_FE_REC); + +ASSYM(PSL_USERSTATIC, PSL_USERSTATIC); +#endif + +ASSYM(PSL_EE, PSL_EE); +ASSYM(PSL_FE0, PSL_FE0); +ASSYM(PSL_FE1, PSL_FE1); +ASSYM(PSL_FP, PSL_FP); +ASSYM(PSL_ME, PSL_ME); +ASSYM(PSL_PR, PSL_PR); +ASSYM(PSL_PMM, PSL_PMM); + +ASSYM(PSL_KERNSET, PSL_KERNSET); +ASSYM(PSL_USERSET, PSL_USERSET); +
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