Date: Fri, 13 May 2016 15:11:17 +0000 (UTC) From: "Bjoern A. Zeeb" <bz@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r299678 - head/sys/x86/x86 Message-ID: <201605131511.u4DFBH5k090190@repo.freebsd.org>
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Author: bz Date: Fri May 13 15:11:17 2016 New Revision: 299678 URL: https://svnweb.freebsd.org/changeset/base/299678 Log: We already turn the AMD erratum383 workaround on for certain VM_GUEST_VM if specific CPU features are not present. Some simulation environments, e.g. gem5, have been found to require more TLB management from the kernel in certain setups. It is currently unclear why. Turning on the workaround_erratum383 seems to help and make problems (panics) go away. Given this is a fairly uncommon environment so far, allowing the workaround to be manually enabled from loader in order to make debugging and comparing traces easier, but also to allow gem5 run FreeBSD in X86 timing mode, seems to be the least intrusive option for now until the issue if fully understood. Sponsored by: DARPA/AFRL Reviewed by: kib, alc (earlier) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D6206 Modified: head/sys/x86/x86/mca.c Modified: head/sys/x86/x86/mca.c ============================================================================== --- head/sys/x86/x86/mca.c Fri May 13 15:09:38 2016 (r299677) +++ head/sys/x86/x86/mca.c Fri May 13 15:11:17 2016 (r299678) @@ -104,7 +104,8 @@ SYSCTL_INT(_hw_mca, OID_AUTO, intel6h_HS "Administrative toggle for logging of spurious corrected errors"); int workaround_erratum383; -SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RD, &workaround_erratum383, 0, +SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RD|CTLFLAG_RDTUN, + &workaround_erratum383, 0, "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?"); static STAILQ_HEAD(, mca_internal) mca_freelist;
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