Date: Mon, 9 Mar 2015 14:46:11 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279811 - in head/sys/arm: arm include Message-ID: <201503091446.t29EkBp3052438@svn.freebsd.org>
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Author: ian Date: Mon Mar 9 14:46:10 2015 New Revision: 279811 URL: https://svnweb.freebsd.org/changeset/base/279811 Log: Add minimum cache line sizes to struct cpuinfo, use them in the new cache maintenance routines. Also add a routine to invalidate the branch cache. Submitted by: Michal Meloun Modified: head/sys/arm/arm/cpuinfo.c head/sys/arm/arm/genassym.c head/sys/arm/include/cpu-v6.h head/sys/arm/include/cpuinfo.h Modified: head/sys/arm/arm/cpuinfo.c ============================================================================== --- head/sys/arm/arm/cpuinfo.c Mon Mar 9 14:42:25 2015 (r279810) +++ head/sys/arm/arm/cpuinfo.c Mon Mar 9 14:46:10 2015 (r279811) @@ -34,7 +34,14 @@ __FBSDID("$FreeBSD$"); #include <machine/cpuinfo.h> #include <machine/cpu-v6.h> -struct cpuinfo cpuinfo; +struct cpuinfo cpuinfo = +{ + /* Use safe defaults for start */ + .dcache_line_size = 32, + .dcache_line_mask = 31, + .icache_line_size = 32, + .icache_line_mask = 31, +}; /* Read and parse CPU id scheme */ void @@ -122,4 +129,10 @@ cpuinfo_init(void) cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF; cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF; cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF; + + /* L1 Cache sizes */ + cpuinfo.dcache_line_size = 1 << (CPU_CT_DMINLINE(cpuinfo.ctr ) + 2); + cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1; + cpuinfo.icache_line_size= 1 << (CPU_CT_IMINLINE(cpuinfo.ctr ) + 2); + cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1; } Modified: head/sys/arm/arm/genassym.c ============================================================================== --- head/sys/arm/arm/genassym.c Mon Mar 9 14:42:25 2015 (r279810) +++ head/sys/arm/arm/genassym.c Mon Mar 9 14:46:10 2015 (r279811) @@ -45,6 +45,7 @@ __FBSDID("$FreeBSD$"); #include <machine/cpu.h> #include <machine/proc.h> #include <machine/cpufunc.h> +#include <machine/cpuinfo.h> #include <machine/pte.h> #include <machine/intr.h> #include <machine/sysarch.h> @@ -146,3 +147,8 @@ ASSYM(MAXCOMLEN, MAXCOMLEN); ASSYM(MAXCPU, MAXCPU); ASSYM(NIRQ, NIRQ); ASSYM(PCPU_SIZE, sizeof(struct pcpu)); + +ASSYM(DCACHE_LINE_SIZE, offsetof(struct cpuinfo, dcache_line_size)); +ASSYM(DCACHE_LINE_MASK, offsetof(struct cpuinfo, dcache_line_mask)); +ASSYM(ICACHE_LINE_SIZE, offsetof(struct cpuinfo, icache_line_size)); +ASSYM(ICACHE_LINE_MASK, offsetof(struct cpuinfo, icache_line_mask)); Modified: head/sys/arm/include/cpu-v6.h ============================================================================== --- head/sys/arm/include/cpu-v6.h Mon Mar 9 14:42:25 2015 (r279810) +++ head/sys/arm/include/cpu-v6.h Mon Mar 9 14:46:10 2015 (r279811) @@ -37,6 +37,9 @@ #define CPU_ASID_KERNEL 0 +vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t); +vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t); + /* * Macros to generate CP15 (system control processor) read/write functions. */ @@ -302,7 +305,7 @@ icache_sync(vm_offset_t sva, vm_size_t s vm_offset_t eva = sva + size; dsb(); - for (va = sva; va < eva; va += arm_dcache_align) { + for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { #if __ARM_ARCH >= 7 && defined SMP _CP15_DCCMVAU(va); #else @@ -332,6 +335,19 @@ icache_inv_all(void) isb(); } +/* Invalidate branch predictor buffer */ +static __inline void +bpb_inv_all(void) +{ +#if __ARM_ARCH >= 7 && defined SMP + _CP15_BPIALLIS(); +#else + _CP15_BPIALL(); +#endif + dsb(); + isb(); +} + /* Write back D-cache to PoU */ static __inline void dcache_wb_pou(vm_offset_t sva, vm_size_t size) @@ -340,7 +356,7 @@ dcache_wb_pou(vm_offset_t sva, vm_size_t vm_offset_t eva = sva + size; dsb(); - for (va = sva; va < eva; va += arm_dcache_align) { + for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { #if __ARM_ARCH >= 7 && defined SMP _CP15_DCCMVAU(va); #else @@ -358,7 +374,7 @@ dcache_inv_poc(vm_offset_t sva, vm_paddr vm_offset_t eva = sva + size; /* invalidate L1 first */ - for (va = sva; va < eva; va += arm_dcache_align) { + for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { _CP15_DCIMVAC(va); } dsb(); @@ -368,7 +384,7 @@ dcache_inv_poc(vm_offset_t sva, vm_paddr dsb(); /* then L1 again */ - for (va = sva; va < eva; va += arm_dcache_align) { + for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { _CP15_DCIMVAC(va); } dsb(); @@ -383,7 +399,7 @@ dcache_wb_poc(vm_offset_t sva, vm_paddr_ dsb(); - for (va = sva; va < eva; va += arm_dcache_align) { + for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { _CP15_DCCMVAC(va); } dsb(); @@ -401,7 +417,7 @@ dcache_wbinv_poc(vm_offset_t sva, vm_pad dsb(); /* write back L1 first */ - for (va = sva; va < eva; va += arm_dcache_align) { + for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { _CP15_DCCMVAC(va); } dsb(); @@ -410,7 +426,7 @@ dcache_wbinv_poc(vm_offset_t sva, vm_pad cpu_l2cache_wbinv_range(pa, size); /* then invalidate L1 */ - for (va = sva; va < eva; va += arm_dcache_align) { + for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { _CP15_DCIMVAC(va); } dsb(); Modified: head/sys/arm/include/cpuinfo.h ============================================================================== --- head/sys/arm/include/cpuinfo.h Mon Mar 9 14:42:25 2015 (r279810) +++ head/sys/arm/include/cpuinfo.h Mon Mar 9 14:46:10 2015 (r279811) @@ -82,6 +82,12 @@ struct cpuinfo { int generic_timer_ext; int virtualization_ext; int security_ext; + + /* L1 cache info */ + int dcache_line_size; + int dcache_line_mask; + int icache_line_size; + int icache_line_mask; }; extern struct cpuinfo cpuinfo;
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