Date: Mon, 5 Jan 2015 20:10:04 -0700 From: Warner Losh <imp@bsdimp.com> To: Adrian Chadd <adrian@FreeBSD.org> Cc: Warner Losh <imp@freebsd.org>, Ian Lepore <ian@freebsd.org>, John Baldwin <jhb@freebsd.org>, "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org> Subject: Re: interrupt muxes, bus memory space and other fun amusing things Message-ID: <9F6D585C-7590-4D25-879B-A76D8A959E01@bsdimp.com> In-Reply-To: <CAJ-VmokGtqFZ=sDUgetwEdoGagR7hz1Rfys_ph%2BnbtdRuFsBNQ@mail.gmail.com> References: <CAJ-Vmo=LqZ6Z9oYU5Usv4rHY4AffZPy4QBqwN4onr2STq5OfMg@mail.gmail.com> <5F7CBB50-6C91-49C9-BF69-301496DDE792@bsdimp.com> <CAJ-VmokGtqFZ=sDUgetwEdoGagR7hz1Rfys_ph%2BnbtdRuFsBNQ@mail.gmail.com>
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--Apple-Mail=_5E74F1EF-78EE-4895-9FE8-3630FEEFDAB6 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 > On Jan 5, 2015, at 1:31 PM, Adrian Chadd <adrian@FreeBSD.org> wrote: >=20 > On 5 January 2015 at 08:41, Warner Losh <imp@bsdimp.com> wrote: >>=20 >>> So if I were Linux, I'd just implement a mux that pretends to = trigger >>> interrupts in a much bigger IRQ space. Ie, they map IP0..IP7 to >>> irq0..7, then they pick another IRQ range for the AHB interrupts, = and >>> another IRQ range for the IP2/IP3 interrupt mux. They have a >>> hard-coded mux that takes care of triggering the software IRQ based = on >>> the hardware interrupt and mux register contents. >>>=20 >>> So, how should I approach this? >>=20 >> Same way. You=E2=80=99d create an interrupt device that registers an = interrupt >> for the mux, then farms it out based on the contents of the = registers. >> The MIPS interrupt handler might need some work (arm did) to >> allow this to happen, but it isn=E2=80=99t super difficult (though = IIRc it is tedious). >=20 > Ok. So I can do that, but then devices hang off of which bus? nexus0? > Or this mux? >=20 > Can I create a mux bus to hang things off of that just pass all the > memory region requests up to the parent bus (nexus in this case) ? The hard part is mapping an interrupt provided by a mux to a resource number. However, we already do this for the =E2=80=98hard wired=E2=80=99 = interrupts that are muxed through APIC or PIC controllers on x86. I fail to see how this is any different, apart (perhaps) from the need to do things = dynamically in some way. Warner --Apple-Mail=_5E74F1EF-78EE-4895-9FE8-3630FEEFDAB6 Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc Content-Type: application/pgp-signature; name=signature.asc Content-Description: Message signed with OpenPGP using GPGMail -----BEGIN PGP SIGNATURE----- Comment: GPGTools - https://gpgtools.org iQIcBAEBCgAGBQJUq1IMAAoJEGwc0Sh9sBEAFyQQAOXZ4xZQwhR3shuyzDifDy25 /F6t4cjbLZbEEWTAoOpTmIVZQkiXplZJ8qQkvzNXVOhYhYFrYTz2NzcGqv2OuWzH /pSz5STyg8llMKgmMQr30ccZamwjmPDKrasqrQJB1dCZnHCzBiJyNRLvSlwHhn4Q WJeRthfvmWduV3Yg8eGvlr0sNX+6Tb1XqmuTFjCZF/vUPQRnLZf/s44rry+ahSHb e6g3zAK+XmprChXgBW2b66q3dZa7kuWAaYepCfGDcjsiPBu957IBsjJ67KO7KGm4 TRs3XKmjL4dzJJ1fxp46B28ZysllkMz2fJ5XBs2QdsxpF1aMG5iGMvPq80RLVo9Q ZWkOPwgAQEQ7Z2cXjKWU3vwAPepx13BoFPKrfc9AXFUpAZ0ZjpXPdlCFb8fK2z0g qRVaTO+5Qz2vO427KDDppNX5b9qDL2CmljWJ/khcEByFjmjl+Jqq6G52nWCyhNBT /tvpsyiF8i/umriNwD3r+/apdexVwYxc8NE5btcjNQ9w96v3N86sFClBTQ9vihj5 zmGaAnN9L1nrHMfK+Z9K9mz0qNJXwGo9INGRsqn3VVS8aRngSwubF74v5AoHo5eB Tza4RfuGA0g2KoRpvpT3EcY7WVRGfeL7evmEbIi3EAEIJ+nmV3oFCDBtdfMqb8zz rMM+aoQh7XGKIfYjl+q+ =zvzM -----END PGP SIGNATURE----- --Apple-Mail=_5E74F1EF-78EE-4895-9FE8-3630FEEFDAB6--
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