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Date:      Mon, 25 Oct 2010 15:31:14 +0000 (UTC)
From:      John Baldwin <jhb@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r214347 - in head/sys: amd64/amd64 i386/i386 i386/isa x86/x86
Message-ID:  <201010251531.o9PFVEDj069515@svn.freebsd.org>
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Author: jhb
Date: Mon Oct 25 15:31:13 2010
New Revision: 214347
URL: http://svn.freebsd.org/changeset/base/214347

Log:
  Use 'saveintr' instead of 'savecrit' or 'eflags' to hold the state returned
  by intr_disable().
  
  Requested by:	bde

Modified:
  head/sys/amd64/amd64/fpu.c
  head/sys/i386/i386/initcpu.c
  head/sys/i386/i386/perfmon.c
  head/sys/i386/isa/npx.c
  head/sys/x86/x86/local_apic.c

Modified: head/sys/amd64/amd64/fpu.c
==============================================================================
--- head/sys/amd64/amd64/fpu.c	Mon Oct 25 15:28:03 2010	(r214346)
+++ head/sys/amd64/amd64/fpu.c	Mon Oct 25 15:31:13 2010	(r214347)
@@ -113,14 +113,14 @@ static	struct savefpu		fpu_initialstate;
 void
 fpuinit(void)
 {
-	register_t savecrit;
+	register_t saveintr;
 	u_int mxcsr;
 	u_short control;
 
 	/*
 	 * It is too early for critical_enter() to work on AP.
 	 */
-	savecrit = intr_disable();
+	saveintr = intr_disable();
 	stop_emulating();
 	fninit();
 	control = __INITIAL_FPUCW__;
@@ -137,7 +137,7 @@ fpuinit(void)
 		bzero(fpu_initialstate.sv_xmm, sizeof(fpu_initialstate.sv_xmm));
 	}
 	start_emulating();
-	intr_restore(savecrit);
+	intr_restore(saveintr);
 }
 
 /*

Modified: head/sys/i386/i386/initcpu.c
==============================================================================
--- head/sys/i386/i386/initcpu.c	Mon Oct 25 15:28:03 2010	(r214346)
+++ head/sys/i386/i386/initcpu.c	Mon Oct 25 15:31:13 2010	(r214347)
@@ -787,14 +787,14 @@ void
 enable_K5_wt_alloc(void)
 {
 	u_int64_t	msr;
-	register_t	savecrit;
+	register_t	saveintr;
 
 	/*
 	 * Write allocate is supported only on models 1, 2, and 3, with
 	 * a stepping of 4 or greater.
 	 */
 	if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
-		savecrit = intr_disable();
+		saveintr = intr_disable();
 		msr = rdmsr(0x83);		/* HWCR */
 		wrmsr(0x83, msr & !(0x10));
 
@@ -825,7 +825,7 @@ enable_K5_wt_alloc(void)
 
 		msr=rdmsr(0x83);
 		wrmsr(0x83, msr|0x10); /* enable write allocate */
-		intr_restore(savecrit);
+		intr_restore(saveintr);
 	}
 }
 

Modified: head/sys/i386/i386/perfmon.c
==============================================================================
--- head/sys/i386/i386/perfmon.c	Mon Oct 25 15:28:03 2010	(r214346)
+++ head/sys/i386/i386/perfmon.c	Mon Oct 25 15:31:13 2010	(r214347)
@@ -128,18 +128,18 @@ perfmon_avail(void)
 int
 perfmon_setup(int pmc, unsigned int control)
 {
-	register_t	savecrit;
+	register_t	saveintr;
 
 	if (pmc < 0 || pmc >= NPMC)
 		return EINVAL;
 
 	perfmon_inuse |= (1 << pmc);
 	control &= ~(PMCF_SYS_FLAGS << 16);
-	savecrit = intr_disable();
+	saveintr = intr_disable();
 	ctl_shadow[pmc] = control;
 	writectl(pmc);
 	wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
-	intr_restore(savecrit);
+	intr_restore(saveintr);
 	return 0;
 }
 
@@ -174,17 +174,17 @@ perfmon_fini(int pmc)
 int
 perfmon_start(int pmc)
 {
-	register_t	savecrit;
+	register_t	saveintr;
 
 	if (pmc < 0 || pmc >= NPMC)
 		return EINVAL;
 
 	if (perfmon_inuse & (1 << pmc)) {
-		savecrit = intr_disable();
+		saveintr = intr_disable();
 		ctl_shadow[pmc] |= (PMCF_EN << 16);
 		wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
 		writectl(pmc);
-		intr_restore(savecrit);
+		intr_restore(saveintr);
 		return 0;
 	}
 	return EBUSY;
@@ -193,17 +193,17 @@ perfmon_start(int pmc)
 int
 perfmon_stop(int pmc)
 {
-	register_t	savecrit;
+	register_t	saveintr;
 
 	if (pmc < 0 || pmc >= NPMC)
 		return EINVAL;
 
 	if (perfmon_inuse & (1 << pmc)) {
-		savecrit = intr_disable();
+		saveintr = intr_disable();
 		pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
 		ctl_shadow[pmc] &= ~(PMCF_EN << 16);
 		writectl(pmc);
-		intr_restore(savecrit);
+		intr_restore(saveintr);
 		return 0;
 	}
 	return EBUSY;

Modified: head/sys/i386/isa/npx.c
==============================================================================
--- head/sys/i386/isa/npx.c	Mon Oct 25 15:28:03 2010	(r214346)
+++ head/sys/i386/isa/npx.c	Mon Oct 25 15:31:13 2010	(r214347)
@@ -343,7 +343,7 @@ void
 npxinit(void)
 {
 	static union savefpu dummy;
-	register_t savecrit;
+	register_t saveintr;
 	u_short control;
 
 	if (!hw_float)
@@ -355,7 +355,7 @@ npxinit(void)
 	 *
 	 * It is too early for critical_enter() to work on AP.
 	 */
-	savecrit = intr_disable();
+	saveintr = intr_disable();
 	npxsave(&dummy);
 	stop_emulating();
 #ifdef CPU_ENABLE_SSE
@@ -366,7 +366,7 @@ npxinit(void)
 	control = __INITIAL_NPXCW__;
 	fldcw(control);
 	start_emulating();
-	intr_restore(savecrit);
+	intr_restore(saveintr);
 }
 
 /*

Modified: head/sys/x86/x86/local_apic.c
==============================================================================
--- head/sys/x86/x86/local_apic.c	Mon Oct 25 15:28:03 2010	(r214346)
+++ head/sys/x86/x86/local_apic.c	Mon Oct 25 15:31:13 2010	(r214347)
@@ -341,12 +341,12 @@ lapic_setup(int boot)
 {
 	struct lapic *la;
 	u_int32_t maxlvt;
-	register_t eflags;
+	register_t saveintr;
 	char buf[MAXCOMLEN + 1];
 
 	la = &lapics[lapic_id()];
 	KASSERT(la->la_present, ("missing APIC structure"));
-	eflags = intr_disable();
+	saveintr = intr_disable();
 	maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
 
 	/* Initialize the TPR to allow all interrupts. */
@@ -393,7 +393,7 @@ lapic_setup(int boot)
 	if (maxlvt >= LVT_CMCI)
 		lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci);
 	    
-	intr_restore(eflags);
+	intr_restore(saveintr);
 }
 
 void
@@ -1415,7 +1415,7 @@ lapic_ipi_wait(int delay)
 void
 lapic_ipi_raw(register_t icrlo, u_int dest)
 {
-	register_t value, eflags;
+	register_t value, saveintr;
 
 	/* XXX: Need more sanity checking of icrlo? */
 	KASSERT(lapic != NULL, ("%s called too early", __func__));
@@ -1425,7 +1425,7 @@ lapic_ipi_raw(register_t icrlo, u_int de
 	    ("%s: reserved bits set in ICR LO register", __func__));
 
 	/* Set destination in ICR HI register if it is being used. */
-	eflags = intr_disable();
+	saveintr = intr_disable();
 	if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
 		value = lapic->icr_hi;
 		value &= ~APIC_ID_MASK;
@@ -1438,7 +1438,7 @@ lapic_ipi_raw(register_t icrlo, u_int de
 	value &= APIC_ICRLO_RESV_MASK;
 	value |= icrlo;
 	lapic->icr_lo = value;
-	intr_restore(eflags);
+	intr_restore(saveintr);
 }
 
 #define	BEFORE_SPIN	1000000

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