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Date:      Tue, 11 Nov 2008 07:59:30 +0000 (UTC)
From:      Kip Macy <kmacy@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-user@freebsd.org
Subject:   svn commit: r184834 - in user/kmacy/HEAD_fast_multi_xmit/sys: amd64/include conf dev/hwpmc i386/include modules/hwpmc sys
Message-ID:  <200811110759.mAB7xUCJ094457@svn.freebsd.org>

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Author: kmacy
Date: Tue Nov 11 07:59:29 2008
New Revision: 184834
URL: http://svn.freebsd.org/changeset/base/184834

Log:
  import Nokia's support for pmc on CORE/CORE2

Modified:
  user/kmacy/HEAD_fast_multi_xmit/sys/amd64/include/pmc_mdep.h
  user/kmacy/HEAD_fast_multi_xmit/sys/conf/files.amd64
  user/kmacy/HEAD_fast_multi_xmit/sys/conf/files.i386
  user/kmacy/HEAD_fast_multi_xmit/sys/dev/hwpmc/hwpmc_x86.c
  user/kmacy/HEAD_fast_multi_xmit/sys/dev/hwpmc/pmc_events.h
  user/kmacy/HEAD_fast_multi_xmit/sys/i386/include/pmc_mdep.h
  user/kmacy/HEAD_fast_multi_xmit/sys/modules/hwpmc/Makefile
  user/kmacy/HEAD_fast_multi_xmit/sys/sys/pmc.h

Modified: user/kmacy/HEAD_fast_multi_xmit/sys/amd64/include/pmc_mdep.h
==============================================================================
--- user/kmacy/HEAD_fast_multi_xmit/sys/amd64/include/pmc_mdep.h	Tue Nov 11 03:36:15 2008	(r184833)
+++ user/kmacy/HEAD_fast_multi_xmit/sys/amd64/include/pmc_mdep.h	Tue Nov 11 07:59:29 2008	(r184834)
@@ -37,11 +37,13 @@
 
 #include <dev/hwpmc/hwpmc_amd.h>
 #include <dev/hwpmc/hwpmc_piv.h>
+#include <dev/hwpmc/hwpmc_ipm.h>
 
 union pmc_md_op_pmcallocate  {
 	struct pmc_md_amd_op_pmcallocate	pm_amd;
 	struct pmc_md_p4_op_pmcallocate		pm_p4;
-	uint64_t				__pad[4];
+	struct pmc_md_ipm_op_pmcallocate	pm_ipm;
+	uint32_t				__pad[7];
 };
 
 /* Logging */
@@ -53,6 +55,7 @@ union pmc_md_op_pmcallocate  {
 union pmc_md_pmc {
 	struct pmc_md_amd_pmc	pm_amd;
 	struct pmc_md_p4_pmc	pm_p4;
+	struct pmc_md_ipm_pmc	pm_ipm;
 };
 
 struct pmc;

Modified: user/kmacy/HEAD_fast_multi_xmit/sys/conf/files.amd64
==============================================================================
--- user/kmacy/HEAD_fast_multi_xmit/sys/conf/files.amd64	Tue Nov 11 03:36:15 2008	(r184833)
+++ user/kmacy/HEAD_fast_multi_xmit/sys/conf/files.amd64	Tue Nov 11 07:59:29 2008	(r184834)
@@ -188,6 +188,7 @@ dev/hptrr/hptrr_os_bsd.c	optional	hptrr
 dev/hptrr/hptrr_osm_bsd.c	optional	hptrr
 dev/hptrr/hptrr_config.c	optional	hptrr
 dev/hwpmc/hwpmc_amd.c		optional	hwpmc
+dev/hwpmc/hwpmc_ipm.c		optional	hwpmc
 dev/hwpmc/hwpmc_piv.c		optional	hwpmc
 dev/hwpmc/hwpmc_x86.c		optional	hwpmc
 dev/k8temp/k8temp.c		optional	k8temp

Modified: user/kmacy/HEAD_fast_multi_xmit/sys/conf/files.i386
==============================================================================
--- user/kmacy/HEAD_fast_multi_xmit/sys/conf/files.i386	Tue Nov 11 03:36:15 2008	(r184833)
+++ user/kmacy/HEAD_fast_multi_xmit/sys/conf/files.i386	Tue Nov 11 07:59:29 2008	(r184834)
@@ -186,6 +186,7 @@ dev/hptrr/hptrr_os_bsd.c	optional hptrr
 dev/hptrr/hptrr_osm_bsd.c	optional hptrr
 dev/hptrr/hptrr_config.c	optional hptrr
 dev/hwpmc/hwpmc_amd.c		optional hwpmc
+dev/hwpmc/hwpmc_ipm.c		optional hwpmc
 dev/hwpmc/hwpmc_pentium.c	optional hwpmc
 dev/hwpmc/hwpmc_piv.c		optional hwpmc
 dev/hwpmc/hwpmc_ppro.c		optional hwpmc

Modified: user/kmacy/HEAD_fast_multi_xmit/sys/dev/hwpmc/hwpmc_x86.c
==============================================================================
--- user/kmacy/HEAD_fast_multi_xmit/sys/dev/hwpmc/hwpmc_x86.c	Tue Nov 11 03:36:15 2008	(r184833)
+++ user/kmacy/HEAD_fast_multi_xmit/sys/dev/hwpmc/hwpmc_x86.c	Tue Nov 11 07:59:29 2008	(r184834)
@@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/apicreg.h>
 #include <machine/pmc_mdep.h>
 #include <machine/md_var.h>
+#include <machine/cpufunc.h>
 
 #include <vm/vm.h>
 #include <vm/vm_param.h>
@@ -287,6 +288,29 @@ pmc_intel_initialize(void)
 		break;
 	}
 #endif
+	/*
+	 * Check whether the CPU supports newer Intel Architectural 
+	 * Performance Monitoring v1 or v2 facilities- i.e, Intel
+	 * Core Solo/Duo processors or Intel Core Microarchitecture
+	 * processor
+	 */
+#if	defined(__i386__) || defined(__amd64__)
+	if ((cputype == -1) && ((cpu_id & 0xFF) >= 0xA)) {
+		uint32_t regs[4], pm_version;
+		/*
+		 * Determine the PM facilities
+		 */
+		do_cpuid(0xA, regs);
+		pm_version = regs[0] & 0xFF;
+		if (pm_version == 0x1) {
+			cputype = PMC_CPU_INTEL_CORE;
+		} else if (pm_version == 0x2) {
+			cputype = PMC_CPU_INTEL_CORE2;
+		} else {
+			printf("IPM unknown version %d\n", pm_version);
+		}
+	}
+#endif
 
 	if ((int) cputype == -1) {
 		printf("pmc: Unknown Intel CPU.\n");
@@ -316,6 +340,11 @@ pmc_intel_initialize(void)
 	case PMC_CPU_INTEL_PIV:
 		error = pmc_initialize_p4(pmc_mdep);
 		break;
+
+	case PMC_CPU_INTEL_CORE:
+	case PMC_CPU_INTEL_CORE2:
+		error = pmc_initialize_ipm(pmc_mdep);
+		break;
 #endif
 
 #if	defined(__i386__)

Modified: user/kmacy/HEAD_fast_multi_xmit/sys/dev/hwpmc/pmc_events.h
==============================================================================
--- user/kmacy/HEAD_fast_multi_xmit/sys/dev/hwpmc/pmc_events.h	Tue Nov 11 03:36:15 2008	(r184833)
+++ user/kmacy/HEAD_fast_multi_xmit/sys/dev/hwpmc/pmc_events.h	Tue Nov 11 07:59:29 2008	(r184834)
@@ -1,5 +1,6 @@
 /*-
  * Copyright (c) 2005  Joseph Koshy
+ * Copyright (c) 2007-2008 Kartikey M Bhatt (Kartikey.Bhatt at nokia dot com)
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -412,8 +413,385 @@ __PMC_EV(P5, STALL_ON_MMX_INSTRUCTION_WR
 #define	PMC_EV_P5_LAST	        \
 	PMC_EV_P5_STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE
 
-#define	__PMC_EV_IAF()	/* Intel architectural fixed function */
-#define	__PMC_EV_IAP()	/* Intel architectural programmable */
+/* Architectural and non-architectural performance events for 
+ * Intel Core solo/duo processors
+ */
+/* Intel architectural programmable */
+#define	__PMC_EV_IAP1()							\
+__PMC_EV(IAP1, UNHALTED_CORE_CYCLES)					\
+__PMC_EV(IAP1, INSTRUCTIONS_RETIRED)					\
+__PMC_EV(IAP1, UNHALTED_REFERENCE_CYCLES)				\
+__PMC_EV(IAP1, LLC_REFERENCE)						\
+__PMC_EV(IAP1, LLC_MISSES)						\
+__PMC_EV(IAP1, BRANCH_INSTRUCTION_RETIRED)				\
+__PMC_EV(IAP1, BRANCH_MISSES_RETIRED)					\
+__PMC_EV(IAP1, LD_BLOCKS)						\
+__PMC_EV(IAP1, SD_DRAINS)						\
+__PMC_EV(IAP1, MISALIGN_MEM_REF)					\
+__PMC_EV(IAP1, SEG_REG_LOADS)						\
+__PMC_EV(IAP1, SSE_PREFNTA_RET)						\
+__PMC_EV(IAP1, SSE_PREFT1_RET)						\
+__PMC_EV(IAP1, SSE_PREFT2_RET)						\
+__PMC_EV(IAP1, SSE_NTSTORES_RET)					\
+__PMC_EV(IAP1, FP_COMPS_OP_EXE)						\
+__PMC_EV(IAP1, FP_ASSIST)						\
+__PMC_EV(IAP1, MUL)							\
+__PMC_EV(IAP1, DIV)							\
+__PMC_EV(IAP1, CYCLES_DIV_BUSY)						\
+__PMC_EV(IAP1, L2_ADS)							\
+__PMC_EV(IAP1, DBUS_BUSY)						\
+__PMC_EV(IAP1, DBUS_BUSY_RD)						\
+__PMC_EV(IAP1, L2_LINES_IN)						\
+__PMC_EV(IAP1, L2_M_LINES_IN)						\
+__PMC_EV(IAP1, L2_LINES_OUT)						\
+__PMC_EV(IAP1, L2_M_LINES_OUT)						\
+__PMC_EV(IAP1, L2_IFETCH)						\
+__PMC_EV(IAP1, L2_LD)							\
+__PMC_EV(IAP1, L2_ST)							\
+__PMC_EV(IAP1, L2_RQSTS)						\
+__PMC_EV(IAP1, L2_REJECT_CYCLES)					\
+__PMC_EV(IAP1, L2_NO_REQUEST_CYCLES)					\
+__PMC_EV(IAP1, EST_TRANS_ALL)						\
+__PMC_EV(IAP1, EST_TRANS_FREQ)						\
+__PMC_EV(IAP1, THERMAL_TRIP)						\
+__PMC_EV(IAP1, NONHLT_REF_CYCLES)					\
+__PMC_EV(IAP1, SERIAL_EXECUTION_CYCLES)					\
+__PMC_EV(IAP1, DCACHE_CACHE_LD)						\
+__PMC_EV(IAP1, DCACHE_CACHE_ST)						\
+__PMC_EV(IAP1, DCACHE_CACHE_LOCK)					\
+__PMC_EV(IAP1, DATA_MEM_REF)						\
+__PMC_EV(IAP1, DATA_MEM_CACHE_REF)					\
+__PMC_EV(IAP1, DCACHE_REPL)						\
+__PMC_EV(IAP1, DCACHE_M_REPL)						\
+__PMC_EV(IAP1, DCACHE_M_EVICT)						\
+__PMC_EV(IAP1, DCACHE_PEND_MISS)					\
+__PMC_EV(IAP1, DTLB_MISS)						\
+__PMC_EV(IAP1, SSE_PREFNTA_MISS)					\
+__PMC_EV(IAP1, SSE_PREFT1_MISS)						\
+__PMC_EV(IAP1, SSE_PREFT2_MISS)						\
+__PMC_EV(IAP1, SSE_NTSTORES_MISS)					\
+__PMC_EV(IAP1, L1_PREF_REQ)						\
+__PMC_EV(IAP1, BUS_REQ_OUTSTANDING)					\
+__PMC_EV(IAP1, BUS_BNR_CLOCKS)						\
+__PMC_EV(IAP1, BUS_DRDY_CLOCKS)						\
+__PMC_EV(IAP1, BUS_LOCK_CLOCKS)						\
+__PMC_EV(IAP1, BUS_DATA_RCV)						\
+__PMC_EV(IAP1, BUS_TRANS_BRD)						\
+__PMC_EV(IAP1, BUS_TRANS_RFO)						\
+__PMC_EV(IAP1, BUS_TRANS_IFETCH)					\
+__PMC_EV(IAP1, BUS_TRANS_INVAL)						\
+__PMC_EV(IAP1, BUS_TRANS_PWR)						\
+__PMC_EV(IAP1, BUS_TRANS_P)						\
+__PMC_EV(IAP1, BUS_TRANS_IO)						\
+__PMC_EV(IAP1, BUS_TRANS_DEF)						\
+__PMC_EV(IAP1, BUS_TRANS_WB)						\
+__PMC_EV(IAP1, BUS_TRANS_BURST)						\
+__PMC_EV(IAP1, BUS_TRANS_MEM)						\
+__PMC_EV(IAP1, BUS_TRANS_ANY)						\
+__PMC_EV(IAP1, BUS_SNOOPS)						\
+__PMC_EV(IAP1, DCU_SNOOP_TO_SHARE)					\
+__PMC_EV(IAP1, BUS_NOT_IN_USE)						\
+__PMC_EV(IAP1, BUS_SNOOP_STALL)						\
+__PMC_EV(IAP1, ICACHE_READS)						\
+__PMC_EV(IAP1, ICACHE_MISSES)						\
+__PMC_EV(IAP1, ITLB_MISSES)						\
+__PMC_EV(IAP1, IFU_MEM_STALL)						\
+__PMC_EV(IAP1, ILD_STALL)						\
+__PMC_EV(IAP1, BR_INST_EXEC)						\
+__PMC_EV(IAP1, BR_MISSP_EXEC)\
+__PMC_EV(IAP1, BR_BAC_MISSP_EXEC)\
+__PMC_EV(IAP1, BR_CND_EXEC)\
+__PMC_EV(IAP1, BR_CND_MISSP_EXEC)\
+__PMC_EV(IAP1, BR_IND_EXEC)\
+__PMC_EV(IAP1, BR_IND_MISSP_EXEC)\
+__PMC_EV(IAP1, BR_RET_EXEC)\
+__PMC_EV(IAP1, BR_RET_MISSP_EXEC)\
+__PMC_EV(IAP1, BR_RET_BAC_MISSP_EXEC)\
+__PMC_EV(IAP1, BR_CALL_EXEC)\
+__PMC_EV(IAP1, BR_CALL_MISSP_EXEC)\
+__PMC_EV(IAP1, BR_IND_CALL_EXEC)\
+__PMC_EV(IAP1, RESOURCE_STALL)\
+__PMC_EV(IAP1, MMX_INSTR_EXEC)\
+__PMC_EV(IAP1, SIMD_INT_SAT_EXEC)\
+__PMC_EV(IAP1, SIMD_INT_PMUL_EXEC)\
+__PMC_EV(IAP1, SIMD_INT_PSFT_EXEC)\
+__PMC_EV(IAP1, SIMD_INT_PCK_EXEC)\
+__PMC_EV(IAP1, SIMD_INT_UPCK_EXEC)\
+__PMC_EV(IAP1, SIMD_INT_PLOG_EXEC)\
+__PMC_EV(IAP1, SIMD_INT_PARI_EXEC)\
+__PMC_EV(IAP1, INSTR_RET)\
+__PMC_EV(IAP1, FP_COMP_INSTR_RET)\
+__PMC_EV(IAP1, UOPS_RET)\
+__PMC_EV(IAP1, SMC_DETECTED)\
+__PMC_EV(IAP1, BR_INSTR_RET)\
+__PMC_EV(IAP1, BR_MISPRED_RET)\
+__PMC_EV(IAP1, CYCLES_INT_MASKED)\
+__PMC_EV(IAP1, CYCLES_INT_PENDING_MASKED)\
+__PMC_EV(IAP1, HW_INT_RX)\
+__PMC_EV(IAP1, BR_TAKEN_RET)\
+__PMC_EV(IAP1, BR_MISPRED_TAKEN_RET)\
+__PMC_EV(IAP1, MMX_FP_TRANS)\
+__PMC_EV(IAP1, FP_MMX_TRANS)\
+__PMC_EV(IAP1, MMX_ASSIST)\
+__PMC_EV(IAP1, MMX_INST_RET)\
+__PMC_EV(IAP1, INSTR_DECODED)\
+__PMC_EV(IAP1, ESP_UOPS)\
+__PMC_EV(IAP1, SIMD_FP_SP_RET)\
+__PMC_EV(IAP1, SIMD_FP_SP_S_RET)\
+__PMC_EV(IAP1, SIMD_FP_DP_P_RET)\
+__PMC_EV(IAP1, SIMD_FP_DP_S_RET)\
+__PMC_EV(IAP1, SIMD_INT_128_RET)\
+__PMC_EV(IAP1, SIMD_FP_SP_P_COMP_RET)\
+__PMC_EV(IAP1, SIMD_FP_SP_S_COMP_RET)\
+__PMC_EV(IAP1, SIMD_FP_DP_P_COMP_RET)\
+__PMC_EV(IAP1, SIMD_FP_DP_S_COMP_RET)\
+__PMC_EV(IAP1, FUSED_UOPS_RET)\
+__PMC_EV(IAP1, FUSED_LD_UOPS_RET)\
+__PMC_EV(IAP1, FUSED_ST_UOPS_RET)\
+__PMC_EV(IAP1, UNFUSION)\
+__PMC_EV(IAP1, BR_INSTR_DECODED)\
+__PMC_EV(IAP1, BTB_MISSES)\
+__PMC_EV(IAP1, BR_BOGUS)\
+__PMC_EV(IAP1, BACLEARS)\
+__PMC_EV(IAP1, PREF_RQSTS_UP)\
+__PMC_EV(IAP1, PREF_RQSTS_DN)
+
+#define	PMC_EV_IAP1_FIRST	PMC_EV_IAP1_UNHALTED_CORE_CYCLES
+#define	PMC_EV_IAP1_LAST	PMC_EV_IAP1_PREF_RQSTS_DN
+
+/*
+ * 3 Fixed Function PMC's associated events available on Intel
+ * Core Microarchitecture processors
+ */
+#define	__PMC_EV_IAF()							\
+__PMC_EV(IAF, INSTRUCTIONS_RETIRED)				\
+__PMC_EV(IAF, UNHALTED_CORE_CYCLES)				\
+__PMC_EV(IAF, UNHALTED_REFERENCE_CYCLES)
+
+#define	PMC_EV_IAF_FIRST	PMC_EV_IAF_INSTRUCTIONS_RETIRED
+#define	PMC_EV_IAF_LAST		PMC_EV_IAF_UNHALTED_REFERENCE_CYCLES
+
+/*
+ * Architectural and non-architectural performance events for processors
+ * based on Intel Core Microarchitecture
+ */
+#define	__PMC_EV_IAP2()							\
+__PMC_EV(IAP2, UNHALTED_CORE_CYCLES)\
+__PMC_EV(IAP2, INSTRUCTIONS_RETIRED)\
+__PMC_EV(IAP2, UNHALTED_REFERENCE_CYCLES)\
+__PMC_EV(IAP2, LLC_REFERENCE)\
+__PMC_EV(IAP2, LLC_MISSES)\
+  __PMC_EV(IAP2, BRANCH_INSTRUCTION_RETIRED)\
+   __PMC_EV(IAP2, BRANCH_MISSES_RETIRED)\
+    __PMC_EV(IAP2, LOAD_BLOCK_STA)\
+    __PMC_EV(IAP2, LOAD_BLOCK_STD)\
+    __PMC_EV(IAP2, LOAD_BLOCK_OVERLAP_STORE)\
+    __PMC_EV(IAP2, LOAD_BLOCK_UNTIL_RETIRE)\
+    __PMC_EV(IAP2, LOAD_BLOCK_L1D)\
+    __PMC_EV(IAP2, SB_DRAIN_CYCLES)\
+    __PMC_EV(IAP2, STORE_BLOCK_ORDER)\
+    __PMC_EV(IAP2, STORE_BLOCK_SNOOP)\
+    __PMC_EV(IAP2, MISALIGN_MEM_REF)\
+    __PMC_EV(IAP2, SEGMENT_REG_LOADS)\
+    __PMC_EV(IAP2, SSE_PRE_EXEC_NTA)\
+    __PMC_EV(IAP2, SSE_PRE_EXEC_L1)\
+    __PMC_EV(IAP2, SSE_PRE_EXEC_L2)\
+    __PMC_EV(IAP2, SSE_PRE_EXEC_STORES)\
+    __PMC_EV(IAP2, DTLB_MISSES_ANY)\
+    __PMC_EV(IAP2, DTLB_MISSES_MISS_LD)\
+    __PMC_EV(IAP2, L0_DTLB_MISSES_MISS_LD)\
+    __PMC_EV(IAP2, DTLB_MISSES_MISS_ST)\
+    __PMC_EV(IAP2, MEMORY_DISAMBIGUATION_RESET)\
+    __PMC_EV(IAP2, MEMORY_DISAMBIGUATION_SUCCESS)\
+    __PMC_EV(IAP2, PAGE_WALKS_COUNT)\
+    __PMC_EV(IAP2, PAGE_WALKS_CYCLES)\
+    __PMC_EV(IAP2, FP_COMP_OPS_EXE)\
+    __PMC_EV(IAP2, FP_ASSIST)\
+    __PMC_EV(IAP2, MUL)\
+    __PMC_EV(IAP2, DIV)\
+    __PMC_EV(IAP2, CYCLES_DIV_BUSY)\
+    __PMC_EV(IAP2, IDLE_DURING_DIV)\
+    __PMC_EV(IAP2, DELAYED_BYPASS_FP)\
+    __PMC_EV(IAP2, DELAYED_BYPASS_SIMD)\
+    __PMC_EV(IAP2, DELAYED_BYPASS_LOAD)\
+    __PMC_EV(IAP2, L2_ADS)\
+    __PMC_EV(IAP2, L2_DBUS_BUSY_RD)\
+    __PMC_EV(IAP2, L2_LINES_IN)\
+    __PMC_EV(IAP2, L2_M_LINES_IN)\
+    __PMC_EV(IAP2, L2_LINES_OUT)\
+    __PMC_EV(IAP2, L2_M_LINES_OUT)\
+    __PMC_EV(IAP2, L2_IFETCH)\
+    __PMC_EV(IAP2, L2_LD)\
+    __PMC_EV(IAP2, L2_ST)\
+    __PMC_EV(IAP2, L2_LOCK)\
+    __PMC_EV(IAP2, L2_RQSTS)\
+    __PMC_EV(IAP2, L2_RQSTS_SELF_DEMAND_I_STATE)\
+    __PMC_EV(IAP2, L2_RQSTS_SELF_DEMAND_MESI)\
+    __PMC_EV(IAP2, L2_REJECT_BUSQ)\
+    __PMC_EV(IAP2, L2_NO_REQ)\
+    __PMC_EV(IAP2, EIST_TRANS)\
+    __PMC_EV(IAP2, THERMAL_TRIP)\
+    __PMC_EV(IAP2, CPU_CLK_UNHALTED_CORE)\
+    __PMC_EV(IAP2, CPU_CLK_UNHALTED_BUS)\
+    __PMC_EV(IAP2, CPU_CLK_UNHALTED_NO_OTHER)\
+    __PMC_EV(IAP2, L1D_CACHE_LD)\
+    __PMC_EV(IAP2, L1D_CACHE_ST)\
+    __PMC_EV(IAP2, L1D_CACHE_LOCK)\
+    __PMC_EV(IAP2, L1D_CACHE_LOCK_DURATION)\
+    __PMC_EV(IAP2, L1D_ALL_REF)\
+    __PMC_EV(IAP2, L1D_ALL_CACHE_REF)\
+    __PMC_EV(IAP2, L1D_REPL)\
+    __PMC_EV(IAP2, L1D_M_REPL)\
+    __PMC_EV(IAP2, L1D_M_EVICT)\
+    __PMC_EV(IAP2, L1D_PEND_MISS)\
+    __PMC_EV(IAP2, L1D_SPLIT_LOADS)\
+    __PMC_EV(IAP2, L1D_SPLIT_STORES)\
+    __PMC_EV(IAP2, SSE_PRE_MISS_NTA)\
+    __PMC_EV(IAP2, SSE_PRE_MISS_L1)\
+    __PMC_EV(IAP2, SSE_PRE_MISS_L2)\
+    __PMC_EV(IAP2, LOAD_HIT_PRE)\
+    __PMC_EV(IAP2, L1D_PREFETCH_REQUESTS)\
+    __PMC_EV(IAP2, BUS_REQUEST_OUTSTANDING)\
+    __PMC_EV(IAP2, BUS_BNR_DRV)\
+    __PMC_EV(IAP2, BUS_DRDY_CLOCKS)\
+    __PMC_EV(IAP2, BUS_LOCK_CLOCKS)\
+    __PMC_EV(IAP2, BUS_DATA_RCV)\
+    __PMC_EV(IAP2, BUS_TRANS_BRD)\
+    __PMC_EV(IAP2, BUS_TRANS_RFO)\
+    __PMC_EV(IAP2, BUS_TRANS_WB)\
+    __PMC_EV(IAP2, BUS_TRANS_IFETCH)\
+    __PMC_EV(IAP2, BUS_TRANS_INVAL)\
+    __PMC_EV(IAP2, BUS_TRANS_PWR)\
+    __PMC_EV(IAP2, BUS_TRANS_P)\
+    __PMC_EV(IAP2, BUS_TRANS_IO)\
+    __PMC_EV(IAP2, BUS_TRANS_DEF)\
+    __PMC_EV(IAP2, BUS_TRANS_BURST)\
+    __PMC_EV(IAP2, BUS_TRANS_MEM)\
+    __PMC_EV(IAP2, BUS_TRANS_ANY)\
+    __PMC_EV(IAP2, EXT_SNOOP)\
+    __PMC_EV(IAP2, CMP_SNOOP)\
+    __PMC_EV(IAP2, BUS_HIT_DRV)\
+    __PMC_EV(IAP2, BUS_HITM_DRV)\
+    __PMC_EV(IAP2, BUSQ_EMPTY)\
+    __PMC_EV(IAP2, SNOOP_STALL_DRV)\
+    __PMC_EV(IAP2, BUS_IO_WAIT)\
+    __PMC_EV(IAP2, L1I_READS)\
+    __PMC_EV(IAP2, L1I_MISSES)\
+    __PMC_EV(IAP2, ITLB_SMALL_MISS)\
+    __PMC_EV(IAP2, ITLB_LARGE_MISS)\
+    __PMC_EV(IAP2, ITLB_FLUSH)\
+    __PMC_EV(IAP2, ITLB_MISSES)\
+    __PMC_EV(IAP2, INST_QUEUE_FULL)\
+    __PMC_EV(IAP2, CYCLES_L1I_MEM_STALLED)\
+    __PMC_EV(IAP2, ILD_STALL)\
+    __PMC_EV(IAP2, BR_INST_EXEC)\
+    __PMC_EV(IAP2, BR_MISSP_EXEC)\
+    __PMC_EV(IAP2, BR_BAC_MISSP_EXEC)\
+    __PMC_EV(IAP2, BR_CND_EXEC)\
+    __PMC_EV(IAP2, BR_CND_MISSP_EXEC)\
+    __PMC_EV(IAP2, BR_IND_EXEC)\
+    __PMC_EV(IAP2, BR_IND_MISSP_EXEC)\
+    __PMC_EV(IAP2, BR_RET_EXEC)\
+    __PMC_EV(IAP2, BR_RET_MISSP_EXEC)\
+    __PMC_EV(IAP2, BR_RET_BAC_MISSP_EXEC)\
+    __PMC_EV(IAP2, BR_CALL_EXEC)\
+    __PMC_EV(IAP2, BR_CALL_MISSP_EXEC)\
+    __PMC_EV(IAP2, BR_IND_CALL_EXEC)\
+    __PMC_EV(IAP2, BR_TKN_BUBBLE_1)\
+    __PMC_EV(IAP2, BR_TKN_BUBBLE_2)\
+    __PMC_EV(IAP2, RS_UOPS_DISPATCHED)\
+    __PMC_EV(IAP2, RS_UOPS_DISPATCHED_PORT0)\
+    __PMC_EV(IAP2, RS_UOPS_DISPATCHED_PORT1)\
+    __PMC_EV(IAP2, RS_UOPS_DISPATCHED_PORT2)\
+    __PMC_EV(IAP2, RS_UOPS_DISPATCHED_PORT3)\
+    __PMC_EV(IAP2, RS_UOPS_DISPATCHED_PORT4)\
+    __PMC_EV(IAP2, RS_UOPS_DISPATCHED_PORT5)\
+    __PMC_EV(IAP2, MACRO_INSTS_DECODED)\
+    __PMC_EV(IAP2, MACRO_INSTS_CISC_DECODED)\
+    __PMC_EV(IAP2, ESP_SYNCH)\
+    __PMC_EV(IAP2, ESP_ADDITIONS)\
+    __PMC_EV(IAP2, SIMD_UOPS_EXEC)\
+    __PMC_EV(IAP2, SIMD_SAT_UOP_EXEC)\
+    __PMC_EV(IAP2, SIMD_UOP_TYPE_EXEC_MUL)\
+    __PMC_EV(IAP2, SIMD_UOP_TYPE_EXEC_SHIFT)\
+    __PMC_EV(IAP2, SIMD_UOP_TYPE_EXEC_PACK)\
+    __PMC_EV(IAP2, SIMD_UOP_TYPE_EXEC_UNPACK)\
+    __PMC_EV(IAP2, SIMD_UOP_TYPE_EXEC_LOGICAL)\
+    __PMC_EV(IAP2, SIMD_UOP_TYPE_EXEC_ARITHMETIC)\
+    __PMC_EV(IAP2, INST_RETIRED_ANY_P)\
+    __PMC_EV(IAP2, INST_RETIRED_LOADS)\
+    __PMC_EV(IAP2, INST_RETIRED_STORES)\
+    __PMC_EV(IAP2, INST_RETIRED_OTHER)\
+    __PMC_EV(IAP2, X87_OPS_RETIRED_FXCH)\
+    __PMC_EV(IAP2, X87_OPS_RETIRED_ANY)\
+    __PMC_EV(IAP2, UOPS_RETIRED_L2_IND_BR)\
+    __PMC_EV(IAP2, UOPS_RETIRED_STD_STA)\
+    __PMC_EV(IAP2, UOPS_RETIRED_MACRO_FUSION)\
+    __PMC_EV(IAP2, UOPS_RETIRED_FUSED)\
+    __PMC_EV(IAP2, UOPS_RETIRED_NON_FUSED)\
+    __PMC_EV(IAP2, UOPS_RETIRED_ANY)\
+    __PMC_EV(IAP2, MACHINE_NUKES_SMC)\
+    __PMC_EV(IAP2, MACHINE_NUKES_MEM_ORDER)\
+    __PMC_EV(IAP2, BR_INST_RETIRED_ANY)\
+    __PMC_EV(IAP2, BR_INST_RETIRED_PRED_NOT_TAKEN)\
+    __PMC_EV(IAP2, BR_INST_RETIRED_MISPRED_NOT_TAKEN)\
+    __PMC_EV(IAP2, BR_INST_RETIRED_PRED_TAKEN)\
+    __PMC_EV(IAP2, BR_INST_RETIRED_MISPRED_TAKEN)\
+    __PMC_EV(IAP2, BR_INST_RETIRED_TAKEN)\
+    __PMC_EV(IAP2, BR_INST_RETIRED_MISPRED)\
+    __PMC_EV(IAP2, CYCLES_INT_MASKED)\
+    __PMC_EV(IAP2, CYCLES_INT_PENDING_AND_MASKED)\
+    __PMC_EV(IAP2, SIMD_INST_RETIRED_PACKED_SINGLE)\
+    __PMC_EV(IAP2, SIMD_INST_RETIRED_SCALAR_SINGLE)\
+    __PMC_EV(IAP2, SIMD_INST_RETIRED_PACKED_DOUBLE)\
+    __PMC_EV(IAP2, SIMD_INST_RETIRED_SCALAR_DOUBLE)\
+    __PMC_EV(IAP2, SIMD_INST_RETIRED_VECTOR)\
+    __PMC_EV(IAP2, SIMD_INST_RETIRED_ANY)\
+    __PMC_EV(IAP2, HW_INT_RCV)\
+    __PMC_EV(IAP2, ITLB_MISS_RETIRED)\
+    __PMC_EV(IAP2, SIMD_COMP_INST_RETIRED_PACKED_SINGLE)\
+    __PMC_EV(IAP2, SIMD_COMP_INST_RETIRED_SCALAR_SINGLE)\
+    __PMC_EV(IAP2, SIMD_COMP_INST_RETIRED_PACKED_DOUBLE)\
+    __PMC_EV(IAP2, SIMD_COMP_INST_RETIRED_SCALAR_DOUBLE)\
+    __PMC_EV(IAP2, MEM_LOAD_RETIRED_L1D_MISS)\
+    __PMC_EV(IAP2, MEM_LOAD_RETIRED_L1D_LINE_MISS)\
+    __PMC_EV(IAP2, MEM_LOAD_RETIRED_L2_MISS)\
+    __PMC_EV(IAP2, MEM_LOAD_RETIRED_L2_LINE_MISS)\
+    __PMC_EV(IAP2, MEM_LOAD_RETIRED_DTLB_MISS)\
+    __PMC_EV(IAP2, FP_MMX_TRANS_TO_MMX)\
+    __PMC_EV(IAP2, FP_MMX_TRANS_TO_FP)\
+    __PMC_EV(IAP2, SIMD_ASSIST)\
+    __PMC_EV(IAP2, SIMD_INST_RETIRED)\
+    __PMC_EV(IAP2, SIMD_SAT_INST_RETIRED)\
+    __PMC_EV(IAP2, RAT_STALLS_ROB_READ_PORT)\
+    __PMC_EV(IAP2, RAT_STALLS_PARTIAL_CYCLES)\
+    __PMC_EV(IAP2, RAT_STALLS_FLAGS)\
+    __PMC_EV(IAP2, RAT_STALLS_FPSW)\
+    __PMC_EV(IAP2, RAT_STALLS_ANY)\
+    __PMC_EV(IAP2, SEG_RENAME_STALLS_ES)\
+    __PMC_EV(IAP2, SEG_RENAME_STALLS_DS)\
+    __PMC_EV(IAP2, SEG_RENAME_STALLS_FS)\
+    __PMC_EV(IAP2, SEG_RENAME_STALLS_GS)\
+    __PMC_EV(IAP2, SEG_RENAME_STALLS_ANY)\
+    __PMC_EV(IAP2, SEG_REG_RENAME_ES)\
+    __PMC_EV(IAP2, SEG_REG_RENAME_DS)\
+    __PMC_EV(IAP2, SEG_REG_RENAME_FS)\
+    __PMC_EV(IAP2, SEG_REG_RENAME_GS)\
+    __PMC_EV(IAP2, SEG_REG_RENAME_ANY)\
+    __PMC_EV(IAP2, RESOURCE_STALLS_ROB_FULL)\
+    __PMC_EV(IAP2, RESOURCE_STALLS_RS_FULL)\
+    __PMC_EV(IAP2, RESOURCE_STALLS_LD_ST)\
+    __PMC_EV(IAP2, RESOURCE_STALLS_FPCW)\
+    __PMC_EV(IAP2, RESOURCE_STALLS_BR_MISS_CLEAR)\
+    __PMC_EV(IAP2, RESOURCE_STALLS_ANY)\
+    __PMC_EV(IAP2, BR_INST_DECODED)\
+    __PMC_EV(IAP2, BOGUS_BR)\
+    __PMC_EV(IAP2, BACLEARS)\
+    __PMC_EV(IAP2, PREF_RQSTS_UP)\
+__PMC_EV(IAP2, PREF_RQSTS_DN)
+
+#define	PMC_EV_IAP2_FIRST	PMC_EV_IAP2_UNHALTED_CORE_CYCLES
+#define	PMC_EV_IAP2_LAST	PMC_EV_IAP2_PREF_RQSTS_DN
 
 /* timestamp counters. */
 #define	__PMC_EV_TSC()							\
@@ -449,16 +827,18 @@ __PMC_EV(P5, STALL_ON_MMX_INSTRUCTION_WR
 	__PMC_EV_K8()				\
 	__PMC_EV_BLOCK(IAF,	0x10000)	\
 	__PMC_EV_IAF()				\
-	__PMC_EV_BLOCK(IAP,	0x10080)	\
-	__PMC_EV_IAP()				\
-	__PMC_EV_BLOCK(P4,	0x11000)	\
+	__PMC_EV_BLOCK(IAP1,	0x10080)	\
+	__PMC_EV_IAP1()				\
+	__PMC_EV_BLOCK(IAP2,	0x11000)	\
+	__PMC_EV_IAP2()				\
+	__PMC_EV_BLOCK(P4,	0x11080)	\
 	__PMC_EV_P4()				\
-	__PMC_EV_BLOCK(P5,	0x11080)	\
+	__PMC_EV_BLOCK(P5,	0x11100)	\
 	__PMC_EV_P5()				\
-	__PMC_EV_BLOCK(P6,	0x11100)	\
+	__PMC_EV_BLOCK(P6,	0x11180)	\
 	__PMC_EV_P6()
 
 #define	PMC_EVENT_FIRST	PMC_EV_TSC_TSC
-#define	PMC_EVENT_LAST	PMC_EV_P6_LAST
+#define	PMC_EVENT_LAST	PMC_EV_IAP2_LAST
 
 #endif /* _DEV_HWPMC_PMC_EVENTS_H_ */

Modified: user/kmacy/HEAD_fast_multi_xmit/sys/i386/include/pmc_mdep.h
==============================================================================
--- user/kmacy/HEAD_fast_multi_xmit/sys/i386/include/pmc_mdep.h	Tue Nov 11 03:36:15 2008	(r184833)
+++ user/kmacy/HEAD_fast_multi_xmit/sys/i386/include/pmc_mdep.h	Tue Nov 11 07:59:29 2008	(r184834)
@@ -48,6 +48,7 @@
 #include <dev/hwpmc/hwpmc_piv.h>
 #include <dev/hwpmc/hwpmc_ppro.h>
 #include <dev/hwpmc/hwpmc_pentium.h>
+#include <dev/hwpmc/hwpmc_ipm.h>
 
 /*
  * Architecture specific extensions to <sys/pmc.h> structures.
@@ -58,7 +59,8 @@ union pmc_md_op_pmcallocate  {
  	struct pmc_md_ppro_op_pmcallocate	pm_ppro;
 	struct pmc_md_pentium_op_pmcallocate	pm_pentium;
 	struct pmc_md_p4_op_pmcallocate		pm_p4;
-	uint64_t				__pad[4];
+	struct pmc_md_ipm_op_pmcallocate	pm_ipm;
+	uint32_t				__pad[7];
 };
 
 /* Logging */
@@ -73,6 +75,7 @@ union pmc_md_pmc  {
 	struct pmc_md_ppro_pmc	pm_ppro;
 	struct pmc_md_pentium_pmc pm_pentium;
 	struct pmc_md_p4_pmc	pm_p4;
+	struct pmc_md_ipm_pmc	pm_ipm;
 };
 
 struct pmc;

Modified: user/kmacy/HEAD_fast_multi_xmit/sys/modules/hwpmc/Makefile
==============================================================================
--- user/kmacy/HEAD_fast_multi_xmit/sys/modules/hwpmc/Makefile	Tue Nov 11 03:36:15 2008	(r184833)
+++ user/kmacy/HEAD_fast_multi_xmit/sys/modules/hwpmc/Makefile	Tue Nov 11 07:59:29 2008	(r184834)
@@ -9,7 +9,7 @@ KMOD=	hwpmc
 SRCS=	hwpmc_mod.c hwpmc_logging.c vnode_if.h
 
 .if ${MACHINE_ARCH} == "amd64"
-SRCS+=	hwpmc_amd.c hwpmc_piv.c hwpmc_x86.c
+SRCS+=	hwpmc_amd.c hwpmc_ipm.c hwpmc_piv.c hwpmc_x86.c
 SRCS+=	device_if.h bus_if.h
 .endif
 
@@ -18,7 +18,8 @@ SRCS+=	hwpmc_arm.c
 .endif
 
 .if ${MACHINE_ARCH} == "i386"
-SRCS+=	hwpmc_amd.c hwpmc_piv.c hwpmc_ppro.c hwpmc_pentium.c hwpmc_x86.c
+SRCS+=	hwpmc_amd.c hwpmc_ipm.c hwpmc_piv.c hwpmc_ppro.c hwpmc_pentium.c 
+SRCS+=	hwpmc_x86.c
 SRCS+=	device_if.h bus_if.h
 .endif
 

Modified: user/kmacy/HEAD_fast_multi_xmit/sys/sys/pmc.h
==============================================================================
--- user/kmacy/HEAD_fast_multi_xmit/sys/sys/pmc.h	Tue Nov 11 03:36:15 2008	(r184833)
+++ user/kmacy/HEAD_fast_multi_xmit/sys/sys/pmc.h	Tue Nov 11 07:59:29 2008	(r184834)
@@ -105,7 +105,8 @@ enum pmc_cputype {
 	__PMC_CLASS(P6)		/* Intel Pentium Pro counters */	\
 	__PMC_CLASS(P4)		/* Intel Pentium-IV counters */		\
 	__PMC_CLASS(IAF)	/* Intel Core2/Atom, fixed function */	\
-	__PMC_CLASS(IAP)	/* Intel Core...Atom, programmable */
+	__PMC_CLASS(IAP1)	/* Intel Core...Atom, programmable */	\
+	__PMC_CLASS(IAP2)	/* Intel Core...Atom, programmable */
 
 enum pmc_class {
 #undef  __PMC_CLASS



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