Date: Sat, 21 Mar 2015 06:00:47 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r280314 - head/sys/mips/atheros Message-ID: <201503210600.t2L60lsI008045@svn.freebsd.org>
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Author: adrian Date: Sat Mar 21 06:00:46 2015 New Revision: 280314 URL: https://svnweb.freebsd.org/changeset/base/280314 Log: add QCA955x PCIe configuration registers. These are /not/ absolute addresses, as the QCA955x SoC has 2 PCIe RC's (and 1 PCIe EP.) Modified: head/sys/mips/atheros/qca955xreg.h Modified: head/sys/mips/atheros/qca955xreg.h ============================================================================== --- head/sys/mips/atheros/qca955xreg.h Sat Mar 21 05:59:45 2015 (r280313) +++ head/sys/mips/atheros/qca955xreg.h Sat Mar 21 06:00:46 2015 (r280314) @@ -205,4 +205,14 @@ #define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) #define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) +/* PCIe control block - relative to PCI_CTRL_BASE0/PCI_CTRL_BASE1 */ + +#define QCA955X_PCI_APP 0x0 +#define QCA955X_PCI_APP_LTSSM_ENABLE (1 << 0) +#define QCA955X_PCI_RESET 0x18 +#define QCA955X_PCI_RESET_LINK_UP (1 << 0) +#define QCA955X_PCI_INTR_STATUS 0x4c +#define QCA955X_PCI_INTR_MASK 0x50 +#define QCA955X_PCI_INTR_DEV0 (1 << 14) + #endif /* __QCA955XREG_H__ */
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