Date: Mon, 2 Feb 2015 08:01:11 +0000 (UTC) From: Rui Paulo <rpaulo@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r278061 - head/sys/arm/ti/am335x Message-ID: <201502020801.t1281BCL015113@svn.freebsd.org>
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Author: rpaulo Date: Mon Feb 2 08:01:10 2015 New Revision: 278061 URL: https://svnweb.freebsd.org/changeset/base/278061 Log: am335x_clk_pruss_activate(): use the L3F clock. The DISP DPLL clock is slower and was making the PRU programs slower on FreeBSD than on Linux. Submitted by: Manuel Stuehn <freebsdnewbie at freenet.de> MFC after: 1 week Modified: head/sys/arm/ti/am335x/am335x_prcm.c Modified: head/sys/arm/ti/am335x/am335x_prcm.c ============================================================================== --- head/sys/arm/ti/am335x/am335x_prcm.c Mon Feb 2 07:42:03 2015 (r278060) +++ head/sys/arm/ti/am335x/am335x_prcm.c Mon Feb 2 08:01:10 2015 (r278061) @@ -502,7 +502,7 @@ am335x_clk_gpio_activate(struct ti_clock /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */ /* set *_CLKCTRL register OPTFCLKEN_GPIO_1_G DBCLK[18] to FCLK_EN(1) */ prcm_write_4(clk_details->clkctrl_reg, 2 | (1 << 18)); - while ((prcm_read_4(clk_details->clkctrl_reg) & + while ((prcm_read_4(clk_details->clkctrl_reg) & (3 | (1 << 18) )) != (2 | (1 << 18))) DELAY(10); @@ -724,11 +724,11 @@ am335x_clk_lcdc_activate(struct ti_clock prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x4); /* Make sure it's in bypass mode */ - while (!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) + while (!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) & (1 << 8))) DELAY(10); - /* + /* * For now set frequency to 99*SYSFREQ/8 which is twice as * HDMI 1080p pixel clock (minimum LCDC freq divisor is 2) */ @@ -738,7 +738,7 @@ am335x_clk_lcdc_activate(struct ti_clock prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x7); int timeout = 10000; - while ((!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) + while ((!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) & (1 << 0))) && timeout--) DELAY(10); @@ -786,9 +786,9 @@ am335x_clk_pruss_activate(struct ti_cloc while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<6)) == 0) DELAY(10); - /* Select DISP DPLL as OCP clock */ - prcm_write_4(CLKSEL_PRUSS_OCP_CLK, 1); - while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 1) + /* Select L3F as OCP clock */ + prcm_write_4(CLKSEL_PRUSS_OCP_CLK, 0); + while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 0) DELAY(10); /* Clear the RESET bit */
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