Date: Fri, 24 Jun 2005 11:58:49 -0700 From: Peter Wemm <peter@wemm.org> To: freebsd-amd64@freebsd.org Cc: Martin Cracauer <cracauer@cons.org> Subject: Re: Athlon64 board with ECC support? Message-ID: <200506241158.50267.peter@wemm.org> In-Reply-To: <20050624100435.A88745@cons.org> References: <200506131616.j5DGGDfr067534@lurza.secnetix.de> <20050624133457.GC65546@dragon.NUXI.org> <20050624100435.A88745@cons.org>
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On Friday 24 June 2005 07:04 am, Martin Cracauer wrote: > David O'Brien wrote on Fri, Jun 24, 2005 at 06:34:57AM -0700: > > On Thu, Jun 23, 2005 at 06:18:56PM -0400, Martin Cracauer wrote: > > > And I suppose the BIOS needs to support it, too, > > > > Correct. > > > > > although it is not > > > clear to me how ECC exceptions are supposed to be routed anyway. > > > Clearly some chip not being CPU or RAM needs to have a say in the > > > exception delivery? Anybody understands how this works? > > > > Why?? The memory controller is on the same die as the CPU. The > > exception is handled w/in the CPU and it never goes out to any > > support chip. > > Hm, so what does the BIOS do if it has the ECC options, exactly? It just enables the bit in the host memory controller and then has to zero all physical memory to initialize the ECC data. > Does it set defaults in the CPU itself? If so it should be possible > to inspect and mess with these settings after startup? Yes, you can read it using the pciconf(8) tool to read the memory controller settings. It is pci device 24 if memory serves correctly. I don't have the info handy. I believe it is the public 'bios/kernel writers guide' on AMD's site that documents the ECC bits. I know I saw it somewhere in their public docs. -- Peter Wemm - peter@wemm.org; peter@FreeBSD.org; peter@yahoo-inc.com "All of this is for nothing if we don't go to the stars" - JMS/B5
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