From owner-svn-src-projects@FreeBSD.ORG Thu May 14 21:27:10 2009 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 3125B10656B2; Thu, 14 May 2009 21:27:10 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 609D98FC13; Thu, 14 May 2009 21:27:03 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n4ELR362002877; Thu, 14 May 2009 21:27:03 GMT (envelope-from gonzo@svn.freebsd.org) Received: (from gonzo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n4ELR3gL002876; Thu, 14 May 2009 21:27:03 GMT (envelope-from gonzo@svn.freebsd.org) Message-Id: <200905142127.n4ELR3gL002876@svn.freebsd.org> From: Oleksandr Tymoshenko Date: Thu, 14 May 2009 21:27:03 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r192120 - projects/mips/sys/mips/atheros X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 May 2009 21:27:14 -0000 Author: gonzo Date: Thu May 14 21:27:03 2009 New Revision: 192120 URL: http://svn.freebsd.org/changeset/base/192120 Log: - Add SPI-related registers Modified: projects/mips/sys/mips/atheros/ar71xxreg.h Modified: projects/mips/sys/mips/atheros/ar71xxreg.h ============================================================================== --- projects/mips/sys/mips/atheros/ar71xxreg.h Thu May 14 21:26:07 2009 (r192119) +++ projects/mips/sys/mips/atheros/ar71xxreg.h Thu May 14 21:27:03 2009 (r192120) @@ -324,4 +324,17 @@ #define DMA_INTR_TX_UNDERRUN (1 << 1) #define DMA_INTR_TX_PKT_SENT (1 << 0) +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_FS 0x00 +#define AR71XX_SPI_CTRL 0x04 +#define SPI_CTRL_REMAP_DISABLE (1 << 6) +#define SPI_CTRL_CLOCK_DIVIDER_MASK ((1 << 6) - 1) +#define AR71XX_SPI_IO_CTRL 0x08 +#define SPI_IO_CTRL_CS2 (1 << 18) +#define SPI_IO_CTRL_CS1 (1 << 17) +#define SPI_IO_CTRL_CS0 (1 << 16) +#define SPI_IO_CTRL_CLK (1 << 8) +#define SPI_IO_CTRL_DO 1 +#define AR71XX_SPI_RDS 0x0C + #endif /* _AR71XX_REG_H_ */