From owner-svn-src-stable-10@FreeBSD.ORG Sun Oct 26 16:02:36 2014 Return-Path: Delivered-To: svn-src-stable-10@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id C10A3887; Sun, 26 Oct 2014 16:02:36 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 943BE835; Sun, 26 Oct 2014 16:02:36 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s9QG2aXk073906; Sun, 26 Oct 2014 16:02:36 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s9QG2aAx073905; Sun, 26 Oct 2014 16:02:36 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201410261602.s9QG2aAx073905@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sun, 26 Oct 2014 16:02:36 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r273694 - stable/10/sys/arm/freescale/imx X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-10@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for only the 10-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 26 Oct 2014 16:02:36 -0000 Author: ian Date: Sun Oct 26 16:02:35 2014 New Revision: 273694 URL: https://svnweb.freebsd.org/changeset/base/273694 Log: MFC r273561: Install a temporary workaround to avoid problems in fdt data with linux's workaround for an imx6 chip erratum by using gpio1_6 as an interrupt. Modified: stable/10/sys/arm/freescale/imx/imx6_machdep.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/freescale/imx/imx6_machdep.c ============================================================================== --- stable/10/sys/arm/freescale/imx/imx6_machdep.c Sun Oct 26 15:28:07 2014 (r273693) +++ stable/10/sys/arm/freescale/imx/imx6_machdep.c Sun Oct 26 16:02:35 2014 (r273694) @@ -53,8 +53,39 @@ struct fdt_fixup_entry fdt_fixup_table[] { NULL, NULL } }; +static uint32_t gpio1_node; + +/* + * Work around the linux workaround for imx6 erratum 006687, in which some + * ethernet interrupts don't go to the GPC and thus won't wake the system from + * Wait mode. We don't use Wait mode (which halts the GIC, leaving only GPC + * interrupts able to wake the system), so we don't experience the bug at all. + * The linux workaround is to reconfigure GPIO1_6 as the ENET interrupt by + * writing magic values to an undocumented IOMUX register, then letting the gpio + * interrupt driver notify the ethernet driver. We'll be able to do all that + * (even though we don't need to) once the INTRNG project is committed and the + * imx_gpio driver becomes an interrupt driver. Until then, this crazy little + * workaround watches for requests to map an interrupt 6 with the interrupt + * controller node referring to gpio1, and it substitutes the proper ffec + * interrupt number. + */ +static int +imx6_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt, + int *trig, int *pol) +{ + + if (fdt32_to_cpu(intr[0]) == 6 && + OF_node_from_xref(iparent) == gpio1_node) { + *interrupt = 150; + *trig = INTR_TRIGGER_CONFORM; + *pol = INTR_POLARITY_CONFORM; + return (0); + } + return (gic_decode_fdt(iparent, intr, interrupt, trig, pol)); +} + fdt_pic_decode_t fdt_pic_table[] = { - &gic_decode_fdt, + &imx6_decode_fdt, NULL }; @@ -83,6 +114,9 @@ void initarm_late_init(void) { + /* Cache the gpio1 node handle for imx6_decode_fdt() workaround code. */ + gpio1_node = OF_node_from_xref( + OF_finddevice("/soc/aips-bus@02000000/gpio@0209c000")); } /*