Date: Wed, 26 Apr 2006 10:11:57 -0700 From: John-Mark Gurney <gurney_j@resnet.uoregon.edu> To: "M. Warner Losh" <imp@bsdimp.com> Cc: scottl@samsco.org, src-committers@FreeBSD.org, bde@zeta.org.au, jhb@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org, mj@feral.com Subject: Re: cvs commit: src/sys/dev/bce if_bcereg.h Message-ID: <20060426171157.GE728@funkthat.com> In-Reply-To: <20060426.102502.11595340.imp@bsdimp.com> References: <20060425223519.F65802@ns1.feral.com> <444F0923.8050508@samsco.org> <20060426.101245.90994186.imp@bsdimp.com> <20060426.102502.11595340.imp@bsdimp.com>
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Warner Losh wrote this message on Wed, Apr 26, 2006 at 10:25 -0600:
> In message: <20060426.101245.90994186.imp@bsdimp.com>
> : bus_size_t is for differences between two bus_addr_t quantities, since
> : it specifies the size of resources on a bus. It is also used for
> : transfer sizes and the like. That's why I think it should be a 64-bit
> : quantity: 64-bit - 64-bit = 64-bit.
>
> I should have added that if there's a substantial penalty for going to
> 64-bits, then we should avoid it. My objections are based on the
> resource allocation perspective, not the DMA segment size perspective.
> It will be a while before video cards have > 4G window of resources
> presented to the system. While an individual DMA transfer on the
> PCI-E bus may not cross such a boundary, I bleieve that individual
> resources can consume more than 4G. Our PCI code doesn't handle BARs
> that are > 4G in size correctly, but it does handle BARs that are
> mapped anywhere in a 64-bit address space.
I have patches (in the sun4v tree) to the pcib code that has it
properly support 64bit addresses...
--
John-Mark Gurney Voice: +1 415 225 5579
"All that I will do, has been done, All that I have, has not."
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