From owner-svn-src-projects@FreeBSD.ORG Mon Apr 27 18:29:59 2009 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6C9E710656C8; Mon, 27 Apr 2009 18:29:59 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 59D2C8FC19; Mon, 27 Apr 2009 18:29:59 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n3RITxgX022656; Mon, 27 Apr 2009 18:29:59 GMT (envelope-from gonzo@svn.freebsd.org) Received: (from gonzo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n3RITxc4022654; Mon, 27 Apr 2009 18:29:59 GMT (envelope-from gonzo@svn.freebsd.org) Message-Id: <200904271829.n3RITxc4022654@svn.freebsd.org> From: Oleksandr Tymoshenko Date: Mon, 27 Apr 2009 18:29:59 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r191577 - in projects/mips/sys/mips: include mips X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Apr 2009 18:29:59 -0000 Author: gonzo Date: Mon Apr 27 18:29:59 2009 New Revision: 191577 URL: http://svn.freebsd.org/changeset/base/191577 Log: - Use naming convention the same as MIPS spec does: eliminate _sel1 sufix and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1 - Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes) Modified: projects/mips/sys/mips/include/cpufunc.h projects/mips/sys/mips/mips/cpu.c Modified: projects/mips/sys/mips/include/cpufunc.h ============================================================================== --- projects/mips/sys/mips/include/cpufunc.h Mon Apr 27 18:27:54 2009 (r191576) +++ projects/mips/sys/mips/include/cpufunc.h Mon Apr 27 18:29:59 2009 (r191577) @@ -183,6 +183,28 @@ mips_wr_ ## n (uint32_t a0) \ mips_barrier(); \ } struct __hack +#define MIPS_RDRW32_COP0_SEL(n,r,s) \ +static __inline uint32_t \ +mips_rd_ ## n ## s(void) \ +{ \ + int v0; \ + __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ + : [v0] "=&r"(v0)); \ + mips_barrier(); \ + return (v0); \ +} \ +static __inline void \ +mips_wr_ ## n ## s(uint32_t a0) \ +{ \ + __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ + __XSTRING(COP0_SYNC)";" \ + "nop;" \ + "nop;" \ + : \ + : [a0] "r"(a0)); \ + mips_barrier(); \ +} struct __hack + #ifdef TARGET_OCTEON static __inline void mips_sync_icache (void) { @@ -197,6 +219,9 @@ static __inline void mips_sync_icache (v MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); +MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 1); +MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 2); +MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 3); MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); @@ -211,26 +236,15 @@ MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); +MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1); +MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2); +MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 3); MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); +MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 1); +MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 2); +MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 3); #undef MIPS_RDRW32_COP0 -#define MIPS_RD_CONFIG_SEL(sel) \ -static __inline uint32_t \ -mips_rd_config_sel##sel(void) \ -{ \ - int v0; \ - __asm __volatile("mfc0 %[v0], $16, " #sel " ;" \ - : [v0] "=&r" (v0)); \ - mips_barrier(); \ - return (v0); \ -} - - -MIPS_RD_CONFIG_SEL(1); -MIPS_RD_CONFIG_SEL(2); -MIPS_RD_CONFIG_SEL(3); -#undef MIPS_RD_CONFIG_SEL - static __inline register_t intr_disable(void) { Modified: projects/mips/sys/mips/mips/cpu.c ============================================================================== --- projects/mips/sys/mips/mips/cpu.c Mon Apr 27 18:27:54 2009 (r191576) +++ projects/mips/sys/mips/mips/cpu.c Mon Apr 27 18:29:59 2009 (r191577) @@ -89,7 +89,7 @@ mips_get_identity(struct mips_cpuinfo *c return; /* Learn TLB size and L1 cache geometry. */ - cfg1 = mips_rd_config_sel1(); + cfg1 = mips_rd_config1(); cpuinfo->tlb_nentries = ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; @@ -226,14 +226,14 @@ cpu_identify(void) if (!(cfg0 & MIPS3_CONFIG_CM)) return; - cfg1 = mips_rd_config_sel1(); + cfg1 = mips_rd_config1(); printf(" Config1=0x%b\n", cfg1, "\20\7COP2\6MDMX\5PerfCount\4WatchRegs\3MIPS16\2EJTAG\1FPU"); /* If config register selection 2 does not exist, exit. */ if (!(cfg1 & MIPS3_CONFIG_CM)) return; - cfg2 = mips_rd_config_sel2(); + cfg2 = mips_rd_config2(); /* * Config2 contains no useful information other then Config3 * existence flag @@ -242,7 +242,7 @@ cpu_identify(void) /* If config register selection 3 does not exist, exit. */ if (!(cfg2 & MIPS3_CONFIG_CM)) return; - cfg3 = mips_rd_config_sel3(); + cfg3 = mips_rd_config3(); /* Print Config3 if it contains any useful info */ if (cfg3 & ~(0x80000000))