Date: Sun, 22 Mar 2015 02:15:10 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r280337 - head/sys/mips/conf Message-ID: <201503220215.t2M2FAD9084914@svn.freebsd.org>
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Author: adrian Date: Sun Mar 22 02:15:09 2015 New Revision: 280337 URL: https://svnweb.freebsd.org/changeset/base/280337 Log: Add initial D-Link DIR-655 (A1) support. This is based on the AP135 design - QCA9558 SoC, 3x3 2GHz wifi, but no 5GHz (11n or 11ac) chip is available. It however still has 128MiB of RAM, 16MiB of NOR flash and the AR8327N gigabit switch - so it's quite a beefy router device. Tested: * Well, a unit, naturally Obtained from: Completely messing up an amazon.com order and getting this instead, and asking "hey, wonder if I could.." Added: head/sys/mips/conf/DIR-655A1 (contents, props changed) head/sys/mips/conf/DIR-655A1.hints (contents, props changed) Added: head/sys/mips/conf/DIR-655A1 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/conf/DIR-655A1 Sun Mar 22 02:15:09 2015 (r280337) @@ -0,0 +1,56 @@ +# +# DIR-655A1 - 3x3 2GHz D-Link AP +# +# This contains a QCA9558 MIPS74k SoC with on-board 3x3 2GHz wifi, +# 128MiB RAM, an AR8327 5-port gigabit ethernet switch. +# +# $FreeBSD$ +# + +# Include the default QCA955x parameters +include "QCA955X_BASE" + +ident DIR-655A1 + +# Override hints with board values +hints "DIR-655A1.hints" + +# Force the board memory - the base AP135 has 128MB RAM +options AR71XX_REALMEM=(128*1024*1024) + +# i2c GPIO bus +#device gpioiic +#device iicbb +#device iicbus +#device iic + +# Options required for miiproxy and mdiobus +options ARGE_MDIO # Export an MDIO bus separate from arge +device miiproxy # MDIO bus <-> MII PHY rendezvous + +device etherswitch +device arswitch + +# read MSDOS formatted disks - USB +#options MSDOSFS + +# Enable the uboot environment stuff rather then the +# redboot stuff. +options AR71XX_ENV_UBOOT + +# uzip - to boot natively from flash +device geom_uncompress +options GEOM_UNCOMPRESS + +# Used for the static uboot partition map +device geom_map + +options AR71XX_ATH_EEPROM +device firmware # Used by the above +options ATH_EEPROM_FIRMWARE + +# Boot off of the rootfs, as defined in the geom_map setup. +options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\" + +# Default to accept +options IPFIREWALL_DEFAULT_TO_ACCEPT Added: head/sys/mips/conf/DIR-655A1.hints ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/conf/DIR-655A1.hints Sun Mar 22 02:15:09 2015 (r280337) @@ -0,0 +1,153 @@ + +# I'm assuming this is an AP135-020. The AP136-010 in openwrt has +# the ethernet ports wired up to the switch in the reverse way. + +# $FreeBSD$ + +# QCA955X_ETH_CFG_RGMII_EN (1 << 0) +hint.qca955x_gmac.0.gmac_cfg=0x1 + +# mdiobus0 on arge0 +hint.argemdio.0.at="nexus0" +hint.argemdio.0.maddr=0x19000000 +hint.argemdio.0.msize=0x1000 +hint.argemdio.0.order=0 + +# mdiobus1 on arge1 - required to bring up arge1? +hint.argemdio.1.at="nexus0" +hint.argemdio.1.maddr=0x1a000000 +hint.argemdio.1.msize=0x1000 +hint.argemdio.1.order=0 + +# AR8327 - connected via mdiobus0 on arge0 +hint.arswitch.0.at="mdio0" +hint.arswitch.0.is_7240=0 # definitely not the internal switch! +hint.arswitch.0.is_9340=0 # not the internal switch! +hint.arswitch.0.numphys=5 # all ports are PHYs +hint.arswitch.0.phy4cpu=0 +hint.arswitch.0.is_rgmii=0 # not needed +hint.arswitch.0.is_gmii=0 # not needed + +# This is where it gets a bit odd. port 0 and port 6 are CPU ports. +# The current code only supports one CPU port. So hm, what should +# we do to hook PAD6 up to be RGMII but a PHY, not a MAC? + +# The other trick - how do we get arge1 (hooked up to GMAC0) to work? +# That's currently supposed to be hooked up to CPU port 0. + +# Other AR8327 configuration parameters + +# AP136-020 parameters + +# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII + +# AR8327_PAD_MAC_SGMII +hint.arswitch.0.pad.0.mode=3 +#hint.arswitch.0.pad.0.rxclk_delay_sel=0 +hint.arswitch.0.pad.0.sgmii_delay_en=1 + +# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII + +# AR8327_PAD_MAC_RGMII +# XXX I think this hooks it up to the internal MAC6 +hint.arswitch.0.pad.6.mode=6 +hint.arswitch.0.pad.6.txclk_delay_en=1 +hint.arswitch.0.pad.6.rxclk_delay_en=1 +# AR8327_CLK_DELAY_SEL1 +hint.arswitch.0.pad.6.txclk_delay_sel=1 +# AR8327_CLK_DELAY_SEL2 +hint.arswitch.0.pad.6.rxclk_delay_sel=2 + +# XXX there's no LED management just yet! +hint.arswitch.0.led.ctrl0=0x00000000 +hint.arswitch.0.led.ctrl1=0xc737c737 +hint.arswitch.0.led.ctrl2=0x00000000 +hint.arswitch.0.led.ctrl3=0x00c30c00 +hint.arswitch.0.led.open_drain=1 + +# force_link=1 is required for the rest of the parameters +# to be configured. +hint.arswitch.0.port.0.force_link=1 +hint.arswitch.0.port.0.speed=1000 +hint.arswitch.0.port.0.duplex=1 +hint.arswitch.0.port.0.txpause=1 +hint.arswitch.0.port.0.rxpause=1 + +# force_link=1 is required for the rest of the parameters +# to be configured. +hint.arswitch.0.port.6.force_link=1 +hint.arswitch.0.port.6.speed=1000 +hint.arswitch.0.port.6.duplex=1 +hint.arswitch.0.port.6.txpause=1 +hint.arswitch.0.port.6.rxpause=1 + +# arge0 - hooked up to AR8327 GMAC6, RGMII +# set at 1000/full to the switch. +# so, lock both sides of this connect up to 1000/full; +# if_arge thus wont change the PLL configuration +# upon a link status change. +hint.arge.0.phymask=0x0 +hint.arge.0.miimode=3 # RGMII +hint.arge.0.media=1000 +hint.arge.0.fduplex=1 +hint.arge.0.pll_1000=0x56000000 + +# MAC for arge0 is the first 6 bytes of the ART +hint.arge.0.eeprommac=0x1fff0000 + +# arge1 - lock up to 1000/full +hint.arge.1.phymask=0x0 +hint.arge.1.media=1000 +hint.arge.1.fduplex=1 +hint.arge.1.miimode=5 # SGMII +hint.arge.1.pll_1000=0x03000101 + +# MAC for arge1 is the second 6 bytes of the ART +hint.arge.1.eeprommac=0x1fff0006 + +# ath0: Where the ART is - last 64k in the flash +hint.ath.0.eepromaddr=0x1fff0000 +hint.ath.0.eepromsize=16384 + +# 256KiB u-boot +hint.map.0.at="flash/spi0" +hint.map.0.start=0x00000000 +hint.map.0.end=0x00040000 # 256k u-boot +hint.map.0.name="u-boot" +hint.map.0.readonly=1 + +# kernel +hint.map.1.at="flash/spi0" +hint.map.1.start=0x00040000 +hint.map.1.end="search:0x00040000:0x10000:.!/bin/sh" +hint.map.1.name="kernel" +hint.map.1.readonly=1 + +# rootfs +hint.map.2.at="flash/spi0" +hint.map.2.start="search:0x00040000:0x10000:.!/bin/sh" +hint.map.2.end=0x007d0000 +hint.map.2.name="rootfs" +hint.map.2.readonly=1 + +# 64KiB cfg +hint.map.3.at="flash/spi0" +hint.map.3.start=0x007d0000 +hint.map.3.end=0x007e0000 +hint.map.3.name="cfg" +hint.map.3.readonly=0 + +# 8256 KiB mib0 +hint.map.4.at="flash/spi0" +hint.map.4.start=0x007e0000 +hint.map.4.end=0x00ff0000 # 64k mib0 +hint.map.4.name="mib0" +hint.map.4.readonly=1 + +# 64KiB ART +# XXX TODO: is this really here? +hint.map.5.at="flash/spi0" +hint.map.5.start=0x00ff0000 +hint.map.5.end=0x01000000 # 64k ART +hint.map.5.name="ART" +hint.map.5.readonly=1
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