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Date:      Sun, 12 Jul 2015 21:35:46 +0000 (UTC)
From:      Zbigniew Bodek <zbb@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org
Subject:   svn commit: r285431 - in vendor-sys/alpine-hal: . dist
Message-ID:  <201507122135.t6CLZkeo046277@repo.freebsd.org>

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Author: zbb
Date: Sun Jul 12 21:35:45 2015
New Revision: 285431
URL: https://svnweb.freebsd.org/changeset/base/285431

Log:
  Introduce Annapurna Labs HAL for Alpine PoC
  
  This commit adds HAL (Hardware Abstraction Layer) code
  for Alpine Platform on Chip from Annapurna Labs.
  Only published files are included.
  
  HAL version: 2.7
  
  Obtained from:  Semihalf
  Sponsored by:   Annapurna Labs

Added:
  vendor-sys/alpine-hal/
  vendor-sys/alpine-hal/dist/
  vendor-sys/alpine-hal/dist/al_hal_common.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_iofic.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_iofic_regs.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_nb_regs.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_pbs_regs.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_pcie.c   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_pcie.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_pcie_axi_reg.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_pcie_interrupts.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_pcie_regs.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_pcie_w_reg.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_plat_services.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_plat_types.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_reg_utils.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_types.h   (contents, props changed)
  vendor-sys/alpine-hal/dist/al_hal_unit_adapter_regs.h   (contents, props changed)

Added: vendor-sys/alpine-hal/dist/al_hal_common.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ vendor-sys/alpine-hal/dist/al_hal_common.h	Sun Jul 12 21:35:45 2015	(r285431)
@@ -0,0 +1,70 @@
+/*-
+********************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_common HAL Common Layer
+ * Includes all common header files used by HAL
+ *  @{
+ * @file   al_hal_common.h
+ *
+ */
+
+#ifndef __AL_HAL_COMMON_H__
+#define __AL_HAL_COMMON_H__
+
+#include "al_hal_plat_types.h"
+#include "al_hal_plat_services.h"
+
+#include "al_hal_types.h"
+#include "al_hal_reg_utils.h"
+
+/* Get the maximal value out of two typed values */
+#define al_max_t(type, x, y) ({		\
+	type __max1 = (x);			\
+	type __max2 = (y);			\
+	__max1 > __max2 ? __max1 : __max2; })
+
+/* Get the minimal value out of two typed values */
+#define al_min_t(type, x, y) ({		\
+	type __min1 = (x);			\
+	type __min2 = (y);			\
+	__min1 < __min2 ? __min1 : __min2; })
+
+/* Get the number of elements in an array */
+#define AL_ARR_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+
+/** @} end of Common group */
+#endif				/* __AL_HAL_COMMON_H__ */

Added: vendor-sys/alpine-hal/dist/al_hal_iofic.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ vendor-sys/alpine-hal/dist/al_hal_iofic.h	Sun Jul 12 21:35:45 2015	(r285431)
@@ -0,0 +1,222 @@
+/*-
+********************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_interrupts Common I/O Fabric Interrupt Controller
+ * This HAL provides the API for programming the Common I/O Fabric Interrupt
+ * Controller (IOFIC) found in most of the units attached to the I/O Fabric of
+ * Alpine platform
+ *  @{
+ * @file   al_hal_iofic.h
+ *
+ * @brief Header file for the interrupt controller that's embedded in various units
+ *
+ */
+
+#ifndef __AL_HAL_IOFIC_H__
+#define __AL_HAL_IOFIC_H__
+
+#include <al_hal_common.h>
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#define AL_IOFIC_MAX_GROUPS	4
+
+/*
+ * Configurations
+ */
+
+/**
+ * Configure the interrupt controller registers, actual interrupts are still
+ * masked at this stage.
+ *
+ * @param regs_base regs pointer to interrupt controller registers
+ * @param group the interrupt group.
+ * @param flags flags of Interrupt Control Register
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_iofic_config(void __iomem *regs_base, int group,
+		   uint32_t flags);
+
+/**
+ * configure the moderation timer resolution for a given group
+ * Applies for both msix and legacy mode.
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param resolution resolution of the timer interval, the resolution determines the rate
+ * of decrementing the interval timer, setting value N means that the interval
+ * timer will be decremented each (N+1) * (0.68) micro seconds.
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_iofic_moder_res_config(void __iomem *regs_base, int group,
+			     uint8_t resolution);
+
+/**
+ * configure the moderation timer interval for a given legacy interrupt group
+ *
+ * @param regs_base regs pointer to unit registers
+ * @param group the interrupt group
+ * @param interval between interrupts in resolution units. 0 disable
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_iofic_legacy_moder_interval_config(void __iomem *regs_base, int group,
+					 uint8_t interval);
+
+/**
+ * configure the moderation timer interval for a given msix vector
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param vector vector index
+ * @param interval interval between interrupts, 0 disable
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
+				       uint8_t vector, uint8_t interval);
+
+/**
+* configure the vmid attributes for a given msix vector.
+*
+* @param group the interrupt group
+* @param vector index
+* @param vmid the vmid value
+* @param vmid_en take vmid from the intc
+*
+* @return 0 on success. -EINVAL otherwise.
+*/
+int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group,
+				       uint8_t vector, uint32_t vmid, uint8_t vmid_en);
+
+/**
+ * return the offset of the unmask register for a given group.
+ * this function can be used when the upper layer wants to directly
+ * access the unmask regiter and bypass the al_iofic_unmask() API.
+ *
+ * @param regs_base regs pointer to unit registers
+ * @param group the interrupt group
+ * @return the offset of the unmask register.
+ */
+uint32_t __iomem * al_iofic_unmask_offset_get(void __iomem *regs_base, int group);
+
+/**
+ * unmask specific interrupts for a given group
+ * this functions guarantees atomic operations, it is performance optimized as
+ * it will not require read-modify-write. The unmask done using the interrupt
+ * mask clear register, so it's safe to call it while the mask is changed by
+ * the HW (auto mask) or another core.
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of interrupts to unmask, set bits will be unmasked.
+ */
+void al_iofic_unmask(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * mask specific interrupts for a given group
+ * this functions modifies interrupt mask register, the callee must make sure
+ * the mask is not changed by another cpu.
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of interrupts to mask, set bits will be masked.
+ */
+void al_iofic_mask(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * read the mask register for a given group
+ * this functions return the interrupt mask register
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ */
+uint32_t al_iofic_read_mask(void __iomem *regs_base, int group);
+
+/**
+ * read interrupt cause register for a given group
+ * this will clear the set bits if the Clear on Read mode enabled.
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ */
+uint32_t al_iofic_read_cause(void __iomem *regs_base, int group);
+
+/**
+ * clear bits in the interrupt cause register for a given group
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of bits to be cleared, set bits will be cleared.
+ */
+void al_iofic_clear_cause(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * set the cause register for a given group
+ * this function set the cause register. It will generate an interrupt (if
+ * the the interrupt isn't masked )
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of bits to be set.
+ */
+void al_iofic_set_cause(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * unmask specific interrupts from aborting the udma a given group
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ * @param mask bitwise of interrupts to mask
+ */
+void al_iofic_abort_mask(void __iomem *regs_base, int group, uint32_t mask);
+
+/**
+ * trigger all interrupts that are waiting for moderation timers to expire
+ *
+ * @param regs_base pointer to unit registers
+ * @param group the interrupt group
+ */
+void al_iofic_interrupt_moderation_reset(void __iomem *regs_base, int group);
+
+#endif
+/** @} end of interrupt controller group */

Added: vendor-sys/alpine-hal/dist/al_hal_iofic_regs.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ vendor-sys/alpine-hal/dist/al_hal_iofic_regs.h	Sun Jul 12 21:35:45 2015	(r285431)
@@ -0,0 +1,127 @@
+/*_
+********************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __AL_HAL_IOFIC_REG_H
+#define __AL_HAL_IOFIC_REG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+struct al_iofic_grp_ctrl {
+	uint32_t int_cause_grp;         /* Interrupt Cause RegisterSet by hardware */
+	uint32_t rsrvd1;
+	uint32_t int_cause_set_grp;     /* Interrupt Cause Set RegisterWriting 1 to a bit in t ... */
+	uint32_t rsrvd2;
+	uint32_t int_mask_grp;          /* Interrupt Mask RegisterIf Auto-mask control bit =TR ... */
+	uint32_t rsrvd3;
+	uint32_t int_mask_clear_grp;    /* Interrupt Mask Clear RegisterUsed when auto-mask co ... */
+	uint32_t rsrvd4;
+	uint32_t int_status_grp;        /* Interrupt status RegisterThis register latch the st ... */
+	uint32_t rsrvd5;
+	uint32_t int_control_grp;       /* Interrupt Control Register */
+	uint32_t rsrvd6;
+	uint32_t int_abort_msk_grp;     /* Interrupt Mask RegisterEach bit in this register ma ... */
+	uint32_t rsrvd7;
+	uint32_t int_log_msk_grp;       /* Interrupt Log RegisterEach bit in this register mas ... */
+	uint32_t rsrvd8;
+};
+
+struct al_iofic_grp_mod {
+	uint32_t grp_int_mod_reg;      /* Interrupt moderation registerDedicated moderation in ... */
+	uint32_t grp_int_vmid_reg;
+};
+
+struct al_iofic_regs {
+	struct al_iofic_grp_ctrl ctrl[0];
+	uint32_t rsrvd1[0x400 >> 2];
+	struct al_iofic_grp_mod grp_int_mod[0][32];
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** int_control_grp register ****/
+/* When Clear_on_Read =1, All bits of  Cause register  ... */
+#define INT_CONTROL_GRP_CLEAR_ON_READ (1 << 0)
+/* (must be set only when MSIX is enabled)When Auto-Ma ... */
+#define INT_CONTROL_GRP_AUTO_MASK (1 << 1)
+/* Auto_Clear (RW)When Auto-Clear =1, the bits in the  ... */
+#define INT_CONTROL_GRP_AUTO_CLEAR (1 << 2)
+/* When Set_on_Posedge =1, the bits in the interrupt c ... */
+#define INT_CONTROL_GRP_SET_ON_POSEDGE (1 << 3)
+/* When Moderation_Reset =1, all Moderation timers ass ... */
+#define INT_CONTROL_GRP_MOD_RST (1 << 4)
+/* When mask_msi_x =1, No MSI-X from this group is sen ... */
+#define INT_CONTROL_GRP_MASK_MSI_X (1 << 5)
+/* MSI-X AWID value, same ID for all cause bits */
+#define INT_CONTROL_GRP_AWID_MASK 0x00000F00
+#define INT_CONTROL_GRP_AWID_SHIFT 8
+/* This value determines the interval between interrup ... */
+#define INT_CONTROL_GRP_MOD_INTV_MASK 0x00FF0000
+#define INT_CONTROL_GRP_MOD_INTV_SHIFT 16
+/* This value determines the Moderation_Timer_Clock sp ... */
+#define INT_CONTROL_GRP_MOD_RES_MASK 0x0F000000
+#define INT_CONTROL_GRP_MOD_RES_SHIFT 24
+
+/**** grp_int_mod_reg register ****/
+/* Interrupt Moderation Interval registerDedicated reg ... */
+#define INT_MOD_INTV_MASK 0x000000FF
+#define INT_MOD_INTV_SHIFT 0
+
+/**** grp_int_vmid_reg register ****/
+/* Interrupt vmid value registerDedicated reg ... */
+#define INT_MSIX_VMID_MASK 0x0000FFFF
+#define INT_MSIX_VMID_SHIFT 0
+/* Interrupt vmid_en value registerDedicated reg ... */
+#define INT_MSIX_VMID_EN_SHIFT 31
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_IOFIC_REG_H */
+
+
+
+

Added: vendor-sys/alpine-hal/dist/al_hal_nb_regs.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ vendor-sys/alpine-hal/dist/al_hal_nb_regs.h	Sun Jul 12 21:35:45 2015	(r285431)
@@ -0,0 +1,1823 @@
+/*-
+********************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_nb_regs.h
+ *
+ * @brief North Bridge service registers
+ *
+ */
+
+#ifndef __AL_HAL_NB_REGS_H__
+#define __AL_HAL_NB_REGS_H__
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+
+
+struct al_nb_global {
+	/* [0x0]  */
+	uint32_t cpus_config;
+	/* [0x4]  */
+	uint32_t cpus_secure;
+	/* [0x8] Force init reset. */
+	uint32_t cpus_init_control;
+	/* [0xc] Force init reset per DECEI mode. */
+	uint32_t cpus_init_status;
+	/* [0x10]  */
+	uint32_t nb_int_cause;
+	/* [0x14]  */
+	uint32_t sev_int_cause;
+	/* [0x18]  */
+	uint32_t pmus_int_cause;
+	/* [0x1c]  */
+	uint32_t sev_mask;
+	/* [0x20]  */
+	uint32_t cpus_hold_reset;
+	/* [0x24]  */
+	uint32_t cpus_software_reset;
+	/* [0x28]  */
+	uint32_t wd_timer0_reset;
+	/* [0x2c]  */
+	uint32_t wd_timer1_reset;
+	/* [0x30]  */
+	uint32_t wd_timer2_reset;
+	/* [0x34]  */
+	uint32_t wd_timer3_reset;
+	/* [0x38]  */
+	uint32_t ddrc_hold_reset;
+	/* [0x3c]  */
+	uint32_t fabric_software_reset;
+	/* [0x40]  */
+	uint32_t cpus_power_ctrl;
+	uint32_t rsrvd_0[7];
+	/* [0x60]  */
+	uint32_t acf_base_high;
+	/* [0x64]  */
+	uint32_t acf_base_low;
+	/* [0x68]  */
+	uint32_t acf_control_override;
+	/* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address  */
+	uint32_t lgic_base_high;
+	/* [0x70] Read-only that reflects CPU Cluster Local GIC base low address   */
+	uint32_t lgic_base_low;
+	/* [0x74] Read-only that reflects the device's IOGIC base high address.  */
+	uint32_t iogic_base_high;
+	/* [0x78] Read-only that reflects IOGIC base low address  */
+	uint32_t iogic_base_low;
+	/* [0x7c]  */
+	uint32_t io_wr_split_control;
+	/* [0x80]  */
+	uint32_t io_rd_rob_control;
+	/* [0x84]  */
+	uint32_t sb_pos_error_log_1;
+	/* [0x88]  */
+	uint32_t sb_pos_error_log_0;
+	/* [0x8c]  */
+	uint32_t c2swb_config;
+	/* [0x90]  */
+	uint32_t msix_error_log;
+	/* [0x94]  */
+	uint32_t error_cause;
+	/* [0x98]  */
+	uint32_t error_mask;
+	uint32_t rsrvd_1;
+	/* [0xa0]  */
+	uint32_t qos_peak_control;
+	/* [0xa4]  */
+	uint32_t qos_set_control;
+	/* [0xa8]  */
+	uint32_t ddr_qos;
+	uint32_t rsrvd_2[9];
+	/* [0xd0]  */
+	uint32_t acf_misc;
+	/* [0xd4]  */
+	uint32_t config_bus_control;
+	uint32_t rsrvd_3[2];
+	/* [0xe0]  */
+	uint32_t pos_id_match;
+	uint32_t rsrvd_4[3];
+	/* [0xf0]  */
+	uint32_t sb_sel_override_awuser;
+	/* [0xf4]  */
+	uint32_t sb_override_awuser;
+	/* [0xf8]  */
+	uint32_t sb_sel_override_aruser;
+	/* [0xfc]  */
+	uint32_t sb_override_aruser;
+	/* [0x100]  */
+	uint32_t cpu_max_pd_timer;
+	/* [0x104]  */
+	uint32_t cpu_max_pu_timer;
+	uint32_t rsrvd_5[2];
+	/* [0x110]  */
+	uint32_t auto_ddr_self_refresh_counter;
+	uint32_t rsrvd_6[3];
+	/* [0x120]  */
+	uint32_t coresight_pd;
+	/* [0x124]  */
+	uint32_t coresight_internal_0;
+	/* [0x128]  */
+	uint32_t coresight_dbgromaddr;
+	/* [0x12c]  */
+	uint32_t coresight_dbgselfaddr;
+	/* [0x130]  */
+	uint32_t coresght_targetid;
+	/* [0x134]  */
+	uint32_t coresght_targetid0;
+	uint32_t rsrvd_7[10];
+	/* [0x160]  */
+	uint32_t sb_force_same_id_cfg_0;
+	/* [0x164]  */
+	uint32_t sb_mstr_force_same_id_sel_0;
+	/* [0x168]  */
+	uint32_t sb_force_same_id_cfg_1;
+	/* [0x16c]  */
+	uint32_t sb_mstr_force_same_id_sel_1;
+	uint32_t rsrvd[932];
+};
+struct al_nb_system_counter {
+	/* [0x0]  */
+	uint32_t cnt_control;
+	/* [0x4]  */
+	uint32_t cnt_base_freq;
+	/* [0x8]  */
+	uint32_t cnt_low;
+	/* [0xc]  */
+	uint32_t cnt_high;
+	/* [0x10]  */
+	uint32_t cnt_init_low;
+	/* [0x14]  */
+	uint32_t cnt_init_high;
+	uint32_t rsrvd[58];
+};
+struct al_nb_rams_control_misc {
+	/* [0x0]  */
+	uint32_t ca15_rf_misc;
+	uint32_t rsrvd_0;
+	/* [0x8]  */
+	uint32_t nb_rf_misc;
+	uint32_t rsrvd[61];
+};
+struct al_nb_ca15_rams_control {
+	/* [0x0]  */
+	uint32_t rf_0;
+	/* [0x4]  */
+	uint32_t rf_1;
+	/* [0x8]  */
+	uint32_t rf_2;
+	uint32_t rsrvd;
+};
+struct al_nb_semaphores {
+	/* [0x0] This configuration is only sampled during reset of the processor */
+	uint32_t lockn;
+};
+struct al_nb_debug {
+	/* [0x0]  */
+	uint32_t ca15_outputs_1;
+	/* [0x4]  */
+	uint32_t ca15_outputs_2;
+	uint32_t rsrvd_0[2];
+	/* [0x10]  */
+	uint32_t cpu_msg[4];
+	/* [0x20]  */
+	uint32_t rsv0_config;
+	/* [0x24]  */
+	uint32_t rsv1_config;
+	uint32_t rsrvd_1[2];
+	/* [0x30]  */
+	uint32_t rsv0_status;
+	/* [0x34]  */
+	uint32_t rsv1_status;
+	uint32_t rsrvd_2[2];
+	/* [0x40]  */
+	uint32_t ddrc;
+	/* [0x44]  */
+	uint32_t ddrc_phy_smode_control;
+	/* [0x48]  */
+	uint32_t ddrc_phy_smode_status;
+	uint32_t rsrvd_3[5];
+	/* [0x60]  */
+	uint32_t pmc;
+	uint32_t rsrvd_4[3];
+	/* [0x70]  */
+	uint32_t cpus_general;
+	/* [0x74]  */
+	uint32_t cpus_general_1;
+	uint32_t rsrvd_5[2];
+	/* [0x80]  */
+	uint32_t cpus_int_out;
+	uint32_t rsrvd_6[3];
+	/* [0x90]  */
+	uint32_t latch_pc_req;
+	uint32_t rsrvd_7;
+	/* [0x98]  */
+	uint32_t latch_pc_low;
+	/* [0x9c]  */
+	uint32_t latch_pc_high;
+	uint32_t rsrvd_8[24];
+	/* [0x100]  */
+	uint32_t track_dump_ctrl;
+	/* [0x104]  */
+	uint32_t track_dump_rdata_0;
+	/* [0x108]  */
+	uint32_t track_dump_rdata_1;
+	uint32_t rsrvd_9[5];
+	/* [0x120]  */
+	uint32_t track_events;
+	uint32_t rsrvd_10[3];
+	/* [0x130]  */
+	uint32_t pos_track_dump_ctrl;
+	/* [0x134]  */
+	uint32_t pos_track_dump_rdata_0;
+	/* [0x138]  */
+	uint32_t pos_track_dump_rdata_1;
+	uint32_t rsrvd_11;
+	/* [0x140]  */
+	uint32_t c2swb_track_dump_ctrl;
+	/* [0x144]  */
+	uint32_t c2swb_track_dump_rdata_0;
+	/* [0x148]  */
+	uint32_t c2swb_track_dump_rdata_1;
+	uint32_t rsrvd_12;
+	/* [0x150]  */
+	uint32_t cpus_track_dump_ctrl;
+	/* [0x154]  */
+	uint32_t cpus_track_dump_rdata_0;
+	/* [0x158]  */
+	uint32_t cpus_track_dump_rdata_1;
+	uint32_t rsrvd_13;
+	/* [0x160]  */
+	uint32_t c2swb_bar_ovrd_high;
+	/* [0x164]  */
+	uint32_t c2swb_bar_ovrd_low;
+	uint32_t rsrvd[38];
+};
+struct al_nb_cpun_config_status {
+	/* [0x0] This configuration is only sampled during reset of the processor. */
+	uint32_t config;
+	/* [0x4] This configuration is only sampled during reset of the processor. */
+	uint32_t config_aarch64;
+	/* [0x8]  */
+	uint32_t local_cause_mask;
+	uint32_t rsrvd_0;
+	/* [0x10]  */
+	uint32_t pmus_cause_mask;
+	/* [0x14]  */
+	uint32_t sei_cause_mask;
+	uint32_t rsrvd_1[2];
+	/* [0x20] Specifies the state of the CPU with reference to power modes. */
+	uint32_t power_ctrl;
+	/* [0x24]  */
+	uint32_t power_status;
+	/* [0x28]  */
+	uint32_t resume_addr_l;
+	/* [0x2c]  */
+	uint32_t resume_addr_h;
+	uint32_t rsrvd_2[4];
+	/* [0x40]  */
+	uint32_t warm_rst_ctl;
+	uint32_t rsrvd_3;
+	/* [0x48]  */
+	uint32_t rvbar_low;
+	/* [0x4c]  */
+	uint32_t rvbar_high;
+	/* [0x50]  */
+	uint32_t pmu_snapshot;
+	uint32_t rsrvd_4[3];
+	/* [0x60]  */
+	uint32_t cpu_msg_in;
+	uint32_t rsrvd[39];
+};
+struct al_nb_mc_pmu {
+	/* [0x0] PMU Global Control Register */
+	uint32_t pmu_control;
+	/* [0x4] PMU Global Control Register */
+	uint32_t overflow;
+	uint32_t rsrvd[62];
+};
+struct al_nb_mc_pmu_counters {
+	/* [0x0] Counter Configuration Register */
+	uint32_t cfg;
+	/* [0x4] Counter Control Register */
+	uint32_t cntl;
+	/* [0x8] Counter Control Register */
+	uint32_t low;
+	/* [0xc] Counter Control Register */
+	uint32_t high;
+	uint32_t rsrvd[4];
+};
+struct al_nb_nb_version {
+	/* [0x0] Northbridge Revision */
+	uint32_t version;
+	uint32_t rsrvd;
+};
+struct al_nb_sriov {
+	/* [0x0]  */
+	uint32_t cpu_vmid[4];
+	uint32_t rsrvd[4];
+};
+struct al_nb_dram_channels {
+	/* [0x0]  */
+	uint32_t dram_0_control;
+	uint32_t rsrvd_0;
+	/* [0x8]  */
+	uint32_t dram_0_status;
+	uint32_t rsrvd_1;
+	/* [0x10]  */
+	uint32_t ddr_int_cause;
+	uint32_t rsrvd_2;
+	/* [0x18]  */
+	uint32_t ddr_cause_mask;
+	uint32_t rsrvd_3;
+	/* [0x20]  */
+	uint32_t address_map;
+	uint32_t rsrvd_4[3];
+	/* [0x30]  */
+	uint32_t reorder_id_mask_0;
+	/* [0x34]  */
+	uint32_t reorder_id_value_0;
+	/* [0x38]  */
+	uint32_t reorder_id_mask_1;
+	/* [0x3c]  */
+	uint32_t reorder_id_value_1;
+	/* [0x40]  */
+	uint32_t reorder_id_mask_2;
+	/* [0x44]  */
+	uint32_t reorder_id_value_2;
+	/* [0x48]  */
+	uint32_t reorder_id_mask_3;
+	/* [0x4c]  */
+	uint32_t reorder_id_value_3;
+	/* [0x50]  */
+	uint32_t mrr_control_status;
+	uint32_t rsrvd[43];
+};
+struct al_nb_ddr_0_mrr {
+	/* [0x0] Counter Configuration Register */
+	uint32_t val;
+};
+struct al_nb_push_packet {
+	/* [0x0]  */
+	uint32_t pp_config;
+	uint32_t rsrvd_0[3];
+	/* [0x10]  */
+	uint32_t pp_ext_awuser;
+	uint32_t rsrvd_1[3];
+	/* [0x20]  */
+	uint32_t pp_base_low;
+	/* [0x24]  */
+	uint32_t pp_base_high;
+	uint32_t rsrvd_2[2];
+	/* [0x30]  */
+	uint32_t pp_sel_awuser;
+	uint32_t rsrvd[51];
+};
+
+struct al_nb_regs {
+	struct al_nb_global global;                             /* [0x0] */
+	struct al_nb_system_counter system_counter;             /* [0x1000] */
+	struct al_nb_rams_control_misc rams_control_misc;       /* [0x1100] */
+	struct al_nb_ca15_rams_control ca15_rams_control[5];    /* [0x1200] */
+	uint32_t rsrvd_0[108];
+	struct al_nb_semaphores semaphores[64];                 /* [0x1400] */
+	uint32_t rsrvd_1[320];
+	struct al_nb_debug debug;                               /* [0x1a00] */
+	uint32_t rsrvd_2[256];
+	struct al_nb_cpun_config_status cpun_config_status[4];  /* [0x2000] */
+	uint32_t rsrvd_3[1792];
+	struct al_nb_mc_pmu mc_pmu;                             /* [0x4000] */
+	struct al_nb_mc_pmu_counters mc_pmu_counters[4];        /* [0x4100] */
+	uint32_t rsrvd_4[160];
+	struct al_nb_nb_version nb_version;                     /* [0x4400] */
+	uint32_t rsrvd_5[126];
+	struct al_nb_sriov sriov;                               /* [0x4600] */
+	uint32_t rsrvd_6[120];
+	struct al_nb_dram_channels dram_channels;               /* [0x4800] */
+	struct al_nb_ddr_0_mrr ddr_0_mrr[9];                    /* [0x4900] */
+	uint32_t rsrvd_7[439];
+	uint32_t rsrvd_8[1024];					/* [0x5000] */
+	struct al_nb_push_packet push_packet;                   /* [0x6000] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** CPUs_Config register ****/
+/* Disable broadcast of barrier onto system bus.
+Connect to Processor Cluster SYSBARDISABLE. */
+#define NB_GLOBAL_CPUS_CONFIG_SYSBARDISABLE (1 << 0)
+/* Enable broadcast of inner shareable transactions from CPUs.
+Connect to Processor Cluster BROADCASTINNER. */
+#define NB_GLOBAL_CPUS_CONFIG_BROADCASTINNER (1 << 1)
+/* Disable broadcast of cache maintenance system bus.
+Connect to Processor Cluster BROADCASTCACHEMAIN */
+#define NB_GLOBAL_CPUS_CONFIG_BROADCASTCACHEMAINT (1 << 2)
+/* Enable broadcast of outer shareable transactions from CPUs.
+Connect to Processor Cluster  BROADCASTOUTER. */
+#define NB_GLOBAL_CPUS_CONFIG_BROADCASTOUTER (1 << 3)
+/* Defines the internal CPU GIC operating frequency ratio with the main CPU clock.
+0x0: 1:1
+0x1: 1:2
+0x2: 1:3
+0x3: 1:4
+
+Note: This is not in used with CA57 */
+#define NB_GLOBAL_CPUS_CONFIG_PERIPHCLKEN_MASK 0x00000030
+#define NB_GLOBAL_CPUS_CONFIG_PERIPHCLKEN_SHIFT 4
+/* Disables the GIC CPU interface logic and routes the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ
+signals directly to the processor:
+0 Enable the GIC CPU interface logic.
+1 Disable the GIC CPU interface logic.
+The processor only samples this signal as it exits reset. */
+#define NB_GLOBAL_CPUS_CONFIG_GIC_DISABLE (1 << 6)
+/* Disable L1 data cache and L2 snoop tag RAMs automatic invalidate on reset functionality  */
+#define NB_GLOBAL_CPUS_CONFIG_DBG_L1_RESET_DISABLE (1 << 7)
+/* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
+Register (MPIDR).
+This signal is only sampled during reset of the processor. */
+#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF1_MASK 0x00FF0000
+#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF1_SHIFT 16
+/* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
+Register (MPIDR).
+This signal is only sampled during reset of the processor.. */
+#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF2_MASK 0xFF000000
+#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF2_SHIFT 24
+
+/**** CPUs_Secure register ****/
+/* DBGEN
+ */
+#define NB_GLOBAL_CPUS_SECURE_DBGEN      (1 << 0)
+/* NIDEN
+ */
+#define NB_GLOBAL_CPUS_SECURE_NIDEN      (1 << 1)
+/* SPIDEN
+ */
+#define NB_GLOBAL_CPUS_SECURE_SPIDEN     (1 << 2)
+/* SPNIDEN
+ */
+#define NB_GLOBAL_CPUS_SECURE_SPNIDEN    (1 << 3)
+/* Disable write access to some secure GIC registers */
+#define NB_GLOBAL_CPUS_SECURE_CFGSDISABLE (1 << 4)
+/* Disable write access to some secure IOGIC registers */
+#define NB_GLOBAL_CPUS_SECURE_IOGIC_CFGSDISABLE (1 << 5)
+
+/**** CPUs_Init_Control register ****/
+/* CPU Init Done
+Specifies which CPUs' inits are done and can exit poreset.
+By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other CPUs.
+If this bit is cleared for a specific CPU, setting it by primary CPU as part of the initialization process will initiate power-on-reset to this specific CPU. */
+#define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_MASK 0x0000000F
+#define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_SHIFT 0
+/* DBGPWRDNREQ Mask
+When CPU does not exist, its DBGPWRDNREQ must be asserted.
+If corresponding mask bit is set, the DBGPWDNREQ is deasserted. */
+#define NB_GLOBAL_CPUS_INIT_CONTROL_DBGPWRDNREQ_MASK_MASK 0x000000F0
+#define NB_GLOBAL_CPUS_INIT_CONTROL_DBGPWRDNREQ_MASK_SHIFT 4
+/* Force CPU init power-on-reset exit.
+For debug purposes only. */
+#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_CPUPOR_MASK 0x00000F00
+#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_CPUPOR_SHIFT 8
+/* Force dbgpwrdup signal high
+If dbgpwrdup is clear on the processor interface it indicates that the process debug resources are not available for APB access. */
+#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_DBGPWRDUP_MASK 0x0000F000
+#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_DBGPWRDUP_SHIFT 12
+
+/**** CPUs_Init_Status register ****/
+/* Specifies which CPUs are enabled in the device configuration.
+sample at rst_cpus_exist[3:0] reset strap. */
+#define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_MASK 0x0000000F
+#define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_SHIFT 0
+
+/**** NB_Int_Cause register ****/
+/*
+ * Each bit corresponds to an IRQ.
+ * value is 1 for level irq, 0 for trigger irq
+ * Level IRQ indices: 12-13, 23, 24, 26-29
+ */
+#define NB_GLOBAL_NB_INT_CAUSE_LEVEL_IRQ_MASK	0x3D803000
+/* Cross trigger interrupt  */
+#define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_MASK 0x0000000F
+#define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_SHIFT 0
+/* Communications channel receive. Receive portion of Data Transfer Register full flag */
+#define NB_GLOBAL_NB_INT_CAUSE_COMMRX_MASK 0x000000F0
+#define NB_GLOBAL_NB_INT_CAUSE_COMMRX_SHIFT 4
+/* Communication channel transmit. Transmit portion of Data Transfer Register empty flag. */
+#define NB_GLOBAL_NB_INT_CAUSE_COMMTX_MASK 0x00000F00
+#define NB_GLOBAL_NB_INT_CAUSE_COMMTX_SHIFT 8
+/* Reserved, read undefined must write as zeros. */
+#define NB_GLOBAL_NB_INT_CAUSE_RESERVED_15_15 (1 << 15)
+/* Error indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of the L2ECTLR clears the error indicator connected to CA15 nAXIERRIRQ. */
+#define NB_GLOBAL_NB_INT_CAUSE_CPU_AXIERRIRQ (1 << 16)
+/* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */
+#define NB_GLOBAL_NB_INT_CAUSE_CPU_INTERRIRQ (1 << 17)
+/* Coherent fabric error summary interrupt */
+#define NB_GLOBAL_NB_INT_CAUSE_ACF_ERRORIRQ (1 << 18)
+/* DDR Controller ECC Correctable error summary interrupt */
+#define NB_GLOBAL_NB_INT_CAUSE_MCTL_ECC_CORR_ERR (1 << 19)
+/* DDR Controller ECC Uncorrectable error summary interrupt */
+#define NB_GLOBAL_NB_INT_CAUSE_MCTL_ECC_UNCORR_ERR (1 << 20)
+/* DRAM parity error interrupt */
+#define NB_GLOBAL_NB_INT_CAUSE_MCTL_PARITY_ERR (1 << 21)
+/* Reserved, not functional */
+#define NB_GLOBAL_NB_INT_CAUSE_MCTL_WDATARAM_PAR (1 << 22)
+/* Error cause summary interrupt */
+#define NB_GLOBAL_NB_INT_CAUSE_ERR_CAUSE_SUM_A0 (1 << 23)

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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