Date: Sun, 20 Jan 2002 17:51:52 -0500 (EST) From: Garrett Wollman <wollman@khavrinen.lcs.mit.edu> To: Peter Jeremy <peter.jeremy@alcatel.com.au> Cc: arch@FreeBSD.ORG Subject: Re: 64 bit counters again Message-ID: <200201202251.g0KMpq032842@khavrinen.lcs.mit.edu> In-Reply-To: <20020121082826.Z72285@gsmx07.alcatel.com.au> References: <mit.lcs.mail.freebsd-arch/3C48A0E7.F97BC01@mindspring.com> <200201190350.g0J3oNN08944@khavrinen.lcs.mit.edu> <3C48FCEF.9190CA08@mindspring.com> <20020121082826.Z72285@gsmx07.alcatel.com.au>
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<<On Mon, 21 Jan 2002 08:28:27 +1100, Peter Jeremy <peter.jeremy@alcatel.com.au> said: > 64-bit equivalents to the above IA32 instruction are: > IA32: > movl mem,%eax > movl 4+mem,%edx > 1: movl reg_lo,%ebx > movl reg_hi,%ecx > addl %eax,%ebx > adcl %edx,%ecx > lock cmpxchg8b mem > jnz 1b Actually, that local label needs to be two instructions earlier. The beauty of this instruction sequence is that it is also atomic with respect to interrupts on the local processor. > I don't know SPARCv9 or IA64, so can't comment on those, but from > Garrett's comments, the IA64 code is similar to the IA32 code and > the SPARCv9 code is similar to the Alpha code. Actually, the SPARC would be similar to the Intel. I think only Alpha and MIPS implemented the LL/SC version of this primitive. -GAWollman To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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