Date: Mon, 19 May 2014 01:21:03 +0000 (UTC) From: Jack F Vogel <jfv@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r266423 - in head/sys: conf dev/i40e modules/i40e Message-ID: <201405190121.s4J1L3qA068339@svn.freebsd.org>
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Author: jfv Date: Mon May 19 01:21:02 2014 New Revision: 266423 URL: http://svnweb.freebsd.org/changeset/base/266423 Log: This is the beta release of the driver for the new Intel 40G Ethernet Controller XL710 Family. This is the core driver, a VF driver called i40evf, will be following soon. Questions or comments to myself or my co-developer Eric Joyner. Cheers! Added: head/sys/dev/i40e/ head/sys/dev/i40e/i40e.h (contents, props changed) head/sys/dev/i40e/i40e_adminq.c (contents, props changed) head/sys/dev/i40e/i40e_adminq.h (contents, props changed) head/sys/dev/i40e/i40e_adminq_cmd.h (contents, props changed) head/sys/dev/i40e/i40e_alloc.h (contents, props changed) head/sys/dev/i40e/i40e_common.c (contents, props changed) head/sys/dev/i40e/i40e_hmc.c (contents, props changed) head/sys/dev/i40e/i40e_hmc.h (contents, props changed) head/sys/dev/i40e/i40e_lan_hmc.c (contents, props changed) head/sys/dev/i40e/i40e_lan_hmc.h (contents, props changed) head/sys/dev/i40e/i40e_nvm.c (contents, props changed) head/sys/dev/i40e/i40e_osdep.c (contents, props changed) head/sys/dev/i40e/i40e_osdep.h (contents, props changed) head/sys/dev/i40e/i40e_pf.h (contents, props changed) head/sys/dev/i40e/i40e_prototype.h (contents, props changed) head/sys/dev/i40e/i40e_register.h (contents, props changed) head/sys/dev/i40e/i40e_register_x710_int.h (contents, props changed) head/sys/dev/i40e/i40e_status.h (contents, props changed) head/sys/dev/i40e/i40e_txrx.c (contents, props changed) head/sys/dev/i40e/i40e_type.h (contents, props changed) head/sys/dev/i40e/i40e_virtchnl.h (contents, props changed) head/sys/dev/i40e/if_i40e.c (contents, props changed) head/sys/modules/i40e/ head/sys/modules/i40e/Makefile (contents, props changed) Modified: head/sys/conf/files Modified: head/sys/conf/files ============================================================================== --- head/sys/conf/files Sun May 18 22:39:01 2014 (r266422) +++ head/sys/conf/files Mon May 19 01:21:02 2014 (r266423) @@ -1417,6 +1417,22 @@ dev/hptiop/hptiop.c optional hptiop scb dev/hwpmc/hwpmc_logging.c optional hwpmc dev/hwpmc/hwpmc_mod.c optional hwpmc dev/hwpmc/hwpmc_soft.c optional hwpmc +dev/i40e/if_i40e.c optional i40e inet \ + compile-with "${NORMAL_C} -I$S/dev/i40e -DSMP" +dev/i40e/i40e_txrx.c optional i40e inet \ + compile-with "${NORMAL_C} -I$S/dev/i40e -DSMP" +dev/i40e/i40e_osdep.c optional i40e inet \ + compile-with "${NORMAL_C} -I$S/dev/i40e -DSMP" +dev/i40e/i40e_nvm.c optional i40e inet \ + compile-with "${NORMAL_C} -I$S/dev/i40e -DSMP" +dev/i40e/i40e_lan_hmc.c optional i40e inet \ + compile-with "${NORMAL_C} -I$S/dev/i40e -DSMP" +dev/i40e/i40e_hmc.c optional i40e inet \ + compile-with "${NORMAL_C} -I$S/dev/i40e -DSMP" +dev/i40e/i40e_common.c optional i40e inet \ + compile-with "${NORMAL_C} -I$S/dev/i40e -DSMP" +dev/i40e/i40e_adminq.c optional i40e inet \ + compile-with "${NORMAL_C} -I$S/dev/i40e -DSMP" dev/ichsmb/ichsmb.c optional ichsmb dev/ichsmb/ichsmb_pci.c optional ichsmb pci dev/ida/ida.c optional ida Added: head/sys/dev/i40e/i40e.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/i40e/i40e.h Mon May 19 01:21:02 2014 (r266423) @@ -0,0 +1,491 @@ +/****************************************************************************** + + Copyright (c) 2013-2014, Intel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +******************************************************************************/ +/*$FreeBSD$*/ + + +#ifndef _I40E_H_ +#define _I40E_H_ + + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/buf_ring.h> +#include <sys/mbuf.h> +#include <sys/protosw.h> +#include <sys/socket.h> +#include <sys/malloc.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/sockio.h> + +#include <net/if.h> +#include <net/if_arp.h> +#include <net/bpf.h> +#include <net/ethernet.h> +#include <net/if_dl.h> +#include <net/if_media.h> + +#include <net/bpf.h> +#include <net/if_types.h> +#include <net/if_vlan_var.h> + +#include <netinet/in_systm.h> +#include <netinet/in.h> +#include <netinet/if_ether.h> +#include <netinet/ip.h> +#include <netinet/ip6.h> +#include <netinet/tcp.h> +#include <netinet/tcp_lro.h> +#include <netinet/udp.h> +#include <netinet/sctp.h> + +#include <machine/in_cksum.h> + +#include <sys/bus.h> +#include <machine/bus.h> +#include <sys/rman.h> +#include <machine/resource.h> +#include <vm/vm.h> +#include <vm/pmap.h> +#include <machine/clock.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pcireg.h> +#include <sys/proc.h> +#include <sys/sysctl.h> +#include <sys/endian.h> +#include <sys/taskqueue.h> +#include <sys/pcpu.h> +#include <sys/smp.h> +#include <machine/smp.h> + +#include "i40e_type.h" +#include "i40e_prototype.h" + +#ifdef I40E_DEBUG +#define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC_FORMAT_ARGS(mac_addr) \ + (mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \ + (mac_addr)[4], (mac_addr)[5] +#define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off") + +// static void i40e_dump_desc(void *, u8, u16); +#endif + +/* Tunables */ + +/* + * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the + * number of tx/rx descriptors allocated by the driver. Increasing this + * value allows the driver to queue more operations. Each descriptor is 16 + * or 32 bytes (configurable in FVL) + */ +#define DEFAULT_RING 1024 +#define PERFORM_RING 2048 +#define MAX_RING 4096 +#define MIN_RING 32 + +/* Alignment for rings */ +#define DBA_ALIGN 128 + +/* + * This parameter controls the maximum no of times the driver will loop in + * the isr. Minimum Value = 1 + */ +#define MAX_LOOP 10 + +/* + * This is the max watchdog interval, ie. the time that can + * pass between any two TX clean operations, such only happening + * when the TX hardware is functioning. + */ +#define I40E_WATCHDOG (10 * hz) + +/* + * This parameters control when the driver calls the routine to reclaim + * transmit descriptors. + */ +#define I40E_TX_CLEANUP_THRESHOLD (que->num_desc / 8) +#define I40E_TX_OP_THRESHOLD (que->num_desc / 32) + +/* Flow control constants */ +#define I40E_FC_PAUSE 0xFFFF +#define I40E_FC_HI 0x20000 +#define I40E_FC_LO 0x10000 + +/* Defines for printing debug information */ +#define DEBUG_INIT 0 +#define DEBUG_IOCTL 0 +#define DEBUG_HW 0 + +#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") +#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) +#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) +#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") +#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) +#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) +#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") +#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) +#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) + +#define MAX_MULTICAST_ADDR 128 + +#define I40E_BAR 3 +#define I40E_ADM_LIMIT 2 +#define I40E_TSO_SIZE 65535 +#define I40E_TX_BUF_SZ ((u32) 1514) +#define I40E_AQ_BUF_SZ ((u32) 4096) +#define I40E_RX_HDR 128 +#define I40E_AQ_LEN 32 +#define I40E_AQ_BUFSZ 4096 +#define I40E_RX_LIMIT 512 +#define I40E_RX_ITR 0 +#define I40E_TX_ITR 1 +#define I40E_ITR_NONE 3 +#define I40E_QUEUE_EOL 0x7FF +#define I40E_MAX_FRAME 0x2600 +#define I40E_MAX_SEGS 32 +#define I40E_MAX_FILTERS 256 /* This is artificial */ +#define I40E_MAX_TX_BUSY 10 + +/* + * Interrupt Moderation parameters + */ +#define I40E_MAX_ITR 0x07FF +#define I40E_ITR_100K 0x0005 +#define I40E_ITR_20K 0x0019 +#define I40E_ITR_8K 0x003E +#define I40E_ITR_4K 0x007A +#define I40E_ITR_DYNAMIC 0x8000 +#define I40E_LOW_LATENCY 0 +#define I40E_AVE_LATENCY 1 +#define I40E_BULK_LATENCY 2 + +/* MacVlan Flags */ +#define I40E_FILTER_USED (u16)(1 << 0) +#define I40E_FILTER_VLAN (u16)(1 << 1) +#define I40E_FILTER_ADD (u16)(1 << 2) +#define I40E_FILTER_DEL (u16)(1 << 3) +#define I40E_FILTER_MC (u16)(1 << 4) + +/* used in the vlan field of the filter when not a vlan */ +#define I40E_VLAN_ANY -1 + +#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) + +/* Misc flags for i40e_vsi.flags */ +#define I40E_FLAGS_KEEP_TSO4 (1 << 0) +#define I40E_FLAGS_KEEP_TSO6 (1 << 1) + +#define I40E_TX_LOCK(_sc) mtx_lock(&(_sc)->mtx) +#define I40E_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) +#define I40E_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) +#define I40E_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx) +#define I40E_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) + +#define I40E_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx) +#define I40E_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) +#define I40E_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) + +/* + ***************************************************************************** + * vendor_info_array + * + * This array contains the list of Subvendor/Subdevice IDs on which the driver + * should load. + * + ***************************************************************************** + */ +typedef struct _i40e_vendor_info_t { + unsigned int vendor_id; + unsigned int device_id; + unsigned int subvendor_id; + unsigned int subdevice_id; + unsigned int index; +} i40e_vendor_info_t; + + +struct i40e_tx_buf { + u32 eop_index; + struct mbuf *m_head; + bus_dmamap_t map; +}; + +struct i40e_rx_buf { + struct mbuf *m_head; + struct mbuf *m_pack; + struct mbuf *fmp; + bus_dmamap_t hmap; + bus_dmamap_t pmap; +}; + +struct i40e_pkt_info { + u16 etype; + u32 elen; + u32 iplen; + struct ip *ip; + struct ip6_hdr *ip6; + struct tcphdr *th; +}; + +/* +** This struct has multiple uses, multicast +** addresses, vlans, and mac filters all use it. +*/ +struct i40e_mac_filter { + SLIST_ENTRY(i40e_mac_filter) next; + u8 macaddr[ETHER_ADDR_LEN]; + s16 vlan; + u16 flags; +}; + + +/* + * The Transmit ring control struct + */ +struct tx_ring { + struct i40e_queue *que; + struct mtx mtx; + int watchdog; + struct i40e_tx_desc *base; + struct i40e_dma_mem dma; + u16 next_avail; + u16 next_to_clean; + u16 atr_rate; + u16 atr_count; + u16 itr; + u16 latency; + struct i40e_tx_buf *buffers; + volatile u16 avail; + u32 cmd; + bus_dma_tag_t tag; + char mtx_name[16]; + struct buf_ring *br; + + /* Soft Stats */ + u32 packets; + u32 bytes; + u64 no_desc; + u64 total_packets; +}; + + +/* + * The Receive ring control struct + */ +struct rx_ring { + struct i40e_queue *que; + struct mtx mtx; + union i40e_rx_desc *base; + struct i40e_dma_mem dma; + struct lro_ctrl lro; + bool lro_enabled; + bool hdr_split; + bool discard; + u16 next_refresh; + u16 next_check; + u16 itr; + u16 latency; + char mtx_name[16]; + struct i40e_rx_buf *buffers; + u32 mbuf_sz; + bus_dma_tag_t htag; + bus_dma_tag_t ptag; + + /* Soft stats */ + u32 packets; + u32 bytes; + + u64 split; + u64 rx_packets; + u64 rx_bytes; + u64 discarded; + u64 not_done; +}; + +/* +** Driver queue struct: this is the interrupt container +** for the associated tx and rx ring pair. +*/ +struct i40e_queue { + struct i40e_vsi *vsi; + u32 me; + u32 msix; /* This queue's MSIX vector */ + u32 eims; /* This queue's EIMS bit */ + struct resource *res; + void *tag; + int num_desc; /* both tx and rx */ + int busy; + struct tx_ring txr; + struct rx_ring rxr; + struct task task; + struct task tx_task; + struct taskqueue *tq; + + /* Queue stats */ + u64 irqs; + u64 tso; + u64 mbuf_defrag_failed; + u64 mbuf_hdr_failed; + u64 mbuf_pkt_failed; + u64 tx_map_avail; + u64 tx_dma_setup; + u64 dropped_pkts; +}; + +/* +** Virtual Station interface: +** there would be one of these per traffic class/type +** for now just one, and its embedded in the pf +*/ +SLIST_HEAD(i40e_ftl_head, i40e_mac_filter); +struct i40e_vsi { + void *back; + struct ifnet *ifp; + struct device *dev; + struct i40e_hw *hw; + struct ifmedia media; + u64 que_mask; + int id; + u16 msix_base; /* station base MSIX vector */ + u16 num_queues; + u16 rx_itr_setting; + u16 tx_itr_setting; + struct i40e_queue *queues; /* head of queues */ + bool link_active; + u16 seid; + u16 max_frame_size; + u32 link_speed; + bool link_up; + u32 fc; /* local flow ctrl setting */ + + /* MAC/VLAN Filter list */ + struct i40e_ftl_head ftl; + + struct i40e_aqc_vsi_properties_data info; + + eventhandler_tag vlan_attach; + eventhandler_tag vlan_detach; + u16 num_vlans; + + /* Per-VSI stats from hardware */ + struct i40e_eth_stats eth_stats; + struct i40e_eth_stats eth_stats_offsets; + bool stat_offsets_loaded; + + /* Driver statistics */ + u64 hw_filters_del; + u64 hw_filters_add; + + /* Misc. */ + u64 flags; +}; + +/* +** Find the number of unrefreshed RX descriptors +*/ +static inline u16 +i40e_rx_unrefreshed(struct i40e_queue *que) +{ + struct rx_ring *rxr = &que->rxr; + + if (rxr->next_check > rxr->next_refresh) + return (rxr->next_check - rxr->next_refresh - 1); + else + return ((que->num_desc + rxr->next_check) - + rxr->next_refresh - 1); +} + +/* +** Find the next available unused filter +*/ +static inline struct i40e_mac_filter * +i40e_get_filter(struct i40e_vsi *vsi) +{ + struct i40e_mac_filter *f; + + // create a new empty filter + f = malloc(sizeof(struct i40e_mac_filter) , M_DEVBUF, M_NOWAIT | M_ZERO); + SLIST_INSERT_HEAD(&vsi->ftl, f, next); + + return (f); +} + +/* +** Compare two ethernet addresses +*/ +static inline bool +cmp_etheraddr(u8 *ea1, u8 *ea2) +{ + bool cmp = FALSE; + + if ((ea1[0] == ea2[0]) && (ea1[1] == ea2[1]) && + (ea1[2] == ea2[2]) && (ea1[3] == ea2[3]) && + (ea1[4] == ea2[4]) && (ea1[5] == ea2[5])) + cmp = TRUE; + + return (cmp); +} + +/* + * Info for stats sysctls + */ +struct i40e_sysctl_info { + u64 *stat; + char *name; + char *description; +}; + +extern int i40e_atr_rate; + + +/********************************************************************* + * TXRX Function prototypes + *********************************************************************/ +int i40e_allocate_tx_data(struct i40e_queue *); +int i40e_allocate_rx_data(struct i40e_queue *); +void i40e_init_tx_ring(struct i40e_queue *); +int i40e_init_rx_ring(struct i40e_queue *); +bool i40e_rxeof(struct i40e_queue *, int); +bool i40e_txeof(struct i40e_queue *); +int i40e_mq_start(struct ifnet *, struct mbuf *); +int i40e_mq_start_locked(struct ifnet *, struct tx_ring *); +void i40e_deferred_mq_start(void *, int); +void i40e_qflush(struct ifnet *); +void i40e_free_vsi(struct i40e_vsi *); +void i40e_free_que_tx(struct i40e_queue *); +void i40e_free_que_rx(struct i40e_queue *); +#ifdef I40E_FDIR +void i40e_atr(struct i40e_queue *, struct tcphdr *, int); +#endif + +#endif /* _I40E_H_ */ Added: head/sys/dev/i40e/i40e_adminq.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/i40e/i40e_adminq.c Mon May 19 01:21:02 2014 (r266423) @@ -0,0 +1,1089 @@ +/****************************************************************************** + + Copyright (c) 2013-2014, Intel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +******************************************************************************/ +/*$FreeBSD$*/ + +#include "i40e_status.h" +#include "i40e_type.h" +#include "i40e_register.h" +#include "i40e_adminq.h" +#include "i40e_prototype.h" + +/** + * i40e_is_nvm_update_op - return TRUE if this is an NVM update operation + * @desc: API request descriptor + **/ +static INLINE bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc) +{ + return (desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_erase) || + desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_update)); +} + +/** + * i40e_adminq_init_regs - Initialize AdminQ registers + * @hw: pointer to the hardware structure + * + * This assumes the alloc_asq and alloc_arq functions have already been called + **/ +static void i40e_adminq_init_regs(struct i40e_hw *hw) +{ + /* set head and tail registers in our local struct */ + if (hw->mac.type == I40E_MAC_VF) { + hw->aq.asq.tail = I40E_VF_ATQT1; + hw->aq.asq.head = I40E_VF_ATQH1; + hw->aq.asq.len = I40E_VF_ATQLEN1; + hw->aq.arq.tail = I40E_VF_ARQT1; + hw->aq.arq.head = I40E_VF_ARQH1; + hw->aq.arq.len = I40E_VF_ARQLEN1; + } else { + hw->aq.asq.tail = I40E_PF_ATQT; + hw->aq.asq.head = I40E_PF_ATQH; + hw->aq.asq.len = I40E_PF_ATQLEN; + hw->aq.arq.tail = I40E_PF_ARQT; + hw->aq.arq.head = I40E_PF_ARQH; + hw->aq.arq.len = I40E_PF_ARQLEN; + } +} + +/** + * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings + * @hw: pointer to the hardware structure + **/ +enum i40e_status_code i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) +{ + enum i40e_status_code ret_code; + + ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, + i40e_mem_atq_ring, + (hw->aq.num_asq_entries * + sizeof(struct i40e_aq_desc)), + I40E_ADMINQ_DESC_ALIGNMENT); + if (ret_code) + return ret_code; + + ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, + (hw->aq.num_asq_entries * + sizeof(struct i40e_asq_cmd_details))); + if (ret_code) { + i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); + return ret_code; + } + + return ret_code; +} + +/** + * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings + * @hw: pointer to the hardware structure + **/ +enum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) +{ + enum i40e_status_code ret_code; + + ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, + i40e_mem_arq_ring, + (hw->aq.num_arq_entries * + sizeof(struct i40e_aq_desc)), + I40E_ADMINQ_DESC_ALIGNMENT); + + return ret_code; +} + +/** + * i40e_free_adminq_asq - Free Admin Queue send rings + * @hw: pointer to the hardware structure + * + * This assumes the posted send buffers have already been cleaned + * and de-allocated + **/ +void i40e_free_adminq_asq(struct i40e_hw *hw) +{ + i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); +} + +/** + * i40e_free_adminq_arq - Free Admin Queue receive rings + * @hw: pointer to the hardware structure + * + * This assumes the posted receive buffers have already been cleaned + * and de-allocated + **/ +void i40e_free_adminq_arq(struct i40e_hw *hw) +{ + i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); +} + +/** + * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue + * @hw: pointer to the hardware structure + **/ +static enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw) +{ + enum i40e_status_code ret_code; + struct i40e_aq_desc *desc; + struct i40e_dma_mem *bi; + int i; + + /* We'll be allocating the buffer info memory first, then we can + * allocate the mapped buffers for the event processing + */ + + /* buffer_info structures do not need alignment */ + ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, + (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); + if (ret_code) + goto alloc_arq_bufs; + hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; + + /* allocate the mapped buffers */ + for (i = 0; i < hw->aq.num_arq_entries; i++) { + bi = &hw->aq.arq.r.arq_bi[i]; + ret_code = i40e_allocate_dma_mem(hw, bi, + i40e_mem_arq_buf, + hw->aq.arq_buf_size, + I40E_ADMINQ_DESC_ALIGNMENT); + if (ret_code) + goto unwind_alloc_arq_bufs; + + /* now configure the descriptors for use */ + desc = I40E_ADMINQ_DESC(hw->aq.arq, i); + + desc->flags = CPU_TO_LE16(I40E_AQ_FLAG_BUF); + if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) + desc->flags |= CPU_TO_LE16(I40E_AQ_FLAG_LB); + desc->opcode = 0; + /* This is in accordance with Admin queue design, there is no + * register for buffer size configuration + */ + desc->datalen = CPU_TO_LE16((u16)bi->size); + desc->retval = 0; + desc->cookie_high = 0; + desc->cookie_low = 0; + desc->params.external.addr_high = + CPU_TO_LE32(I40E_HI_DWORD(bi->pa)); + desc->params.external.addr_low = + CPU_TO_LE32(I40E_LO_DWORD(bi->pa)); + desc->params.external.param0 = 0; + desc->params.external.param1 = 0; + } + +alloc_arq_bufs: + return ret_code; + +unwind_alloc_arq_bufs: + /* don't try to free the one that failed... */ + i--; + for (; i >= 0; i--) + i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); + i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); + + return ret_code; +} + +/** + * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue + * @hw: pointer to the hardware structure + **/ +static enum i40e_status_code i40e_alloc_asq_bufs(struct i40e_hw *hw) +{ + enum i40e_status_code ret_code; + struct i40e_dma_mem *bi; + int i; + + /* No mapped memory needed yet, just the buffer info structures */ + ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, + (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); + if (ret_code) + goto alloc_asq_bufs; + hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; + + /* allocate the mapped buffers */ + for (i = 0; i < hw->aq.num_asq_entries; i++) { + bi = &hw->aq.asq.r.asq_bi[i]; + ret_code = i40e_allocate_dma_mem(hw, bi, + i40e_mem_asq_buf, + hw->aq.asq_buf_size, + I40E_ADMINQ_DESC_ALIGNMENT); + if (ret_code) + goto unwind_alloc_asq_bufs; + } +alloc_asq_bufs: + return ret_code; + +unwind_alloc_asq_bufs: + /* don't try to free the one that failed... */ + i--; + for (; i >= 0; i--) + i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); + i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); + + return ret_code; +} + +/** + * i40e_free_arq_bufs - Free receive queue buffer info elements + * @hw: pointer to the hardware structure + **/ +static void i40e_free_arq_bufs(struct i40e_hw *hw) +{ + int i; + + /* free descriptors */ + for (i = 0; i < hw->aq.num_arq_entries; i++) + i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); + + /* free the descriptor memory */ + i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); + + /* free the dma header */ + i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); +} + +/** + * i40e_free_asq_bufs - Free send queue buffer info elements + * @hw: pointer to the hardware structure + **/ +static void i40e_free_asq_bufs(struct i40e_hw *hw) +{ + int i; + + /* only unmap if the address is non-NULL */ + for (i = 0; i < hw->aq.num_asq_entries; i++) + if (hw->aq.asq.r.asq_bi[i].pa) + i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); + + /* free the buffer info list */ + i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); + + /* free the descriptor memory */ + i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); + + /* free the dma header */ + i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); +} + +/** + * i40e_config_asq_regs - configure ASQ registers + * @hw: pointer to the hardware structure + * + * Configure base address and length registers for the transmit queue + **/ +static enum i40e_status_code i40e_config_asq_regs(struct i40e_hw *hw) +{ + enum i40e_status_code ret_code = I40E_SUCCESS; + u32 reg = 0; + + /* Clear Head and Tail */ + wr32(hw, hw->aq.asq.head, 0); + wr32(hw, hw->aq.asq.tail, 0); + + if (hw->mac.type == I40E_MAC_VF) { + /* configure the transmit queue */ + wr32(hw, I40E_VF_ATQBAH1, + I40E_HI_DWORD(hw->aq.asq.desc_buf.pa)); + wr32(hw, I40E_VF_ATQBAL1, + I40E_LO_DWORD(hw->aq.asq.desc_buf.pa)); + wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries | + I40E_VF_ATQLEN1_ATQENABLE_MASK)); + reg = rd32(hw, I40E_VF_ATQBAL1); + } else { + /* configure the transmit queue */ + wr32(hw, I40E_PF_ATQBAH, + I40E_HI_DWORD(hw->aq.asq.desc_buf.pa)); + wr32(hw, I40E_PF_ATQBAL, + I40E_LO_DWORD(hw->aq.asq.desc_buf.pa)); + wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries | + I40E_PF_ATQLEN_ATQENABLE_MASK)); + reg = rd32(hw, I40E_PF_ATQBAL); + } + + /* Check one register to verify that config was applied */ + if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa)) + ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; + + return ret_code; +} + +/** + * i40e_config_arq_regs - ARQ register configuration + * @hw: pointer to the hardware structure + * + * Configure base address and length registers for the receive (event queue) + **/ +static enum i40e_status_code i40e_config_arq_regs(struct i40e_hw *hw) +{ + enum i40e_status_code ret_code = I40E_SUCCESS; + u32 reg = 0; + + /* Clear Head and Tail */ + wr32(hw, hw->aq.arq.head, 0); + wr32(hw, hw->aq.arq.tail, 0); + + if (hw->mac.type == I40E_MAC_VF) { + /* configure the receive queue */ + wr32(hw, I40E_VF_ARQBAH1, + I40E_HI_DWORD(hw->aq.arq.desc_buf.pa)); + wr32(hw, I40E_VF_ARQBAL1, + I40E_LO_DWORD(hw->aq.arq.desc_buf.pa)); + wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries | + I40E_VF_ARQLEN1_ARQENABLE_MASK)); + reg = rd32(hw, I40E_VF_ARQBAL1); + } else { + /* configure the receive queue */ + wr32(hw, I40E_PF_ARQBAH, + I40E_HI_DWORD(hw->aq.arq.desc_buf.pa)); + wr32(hw, I40E_PF_ARQBAL, + I40E_LO_DWORD(hw->aq.arq.desc_buf.pa)); + wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries | + I40E_PF_ARQLEN_ARQENABLE_MASK)); + reg = rd32(hw, I40E_PF_ARQBAL); + } + + /* Update tail in the HW to post pre-allocated buffers */ + wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); + + /* Check one register to verify that config was applied */ + if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa)) + ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; + + return ret_code; +} + +/** + * i40e_init_asq - main initialization routine for ASQ + * @hw: pointer to the hardware structure + * + * This is the main initialization routine for the Admin Send Queue + * Prior to calling this function, drivers *MUST* set the following fields + * in the hw->aq structure: + * - hw->aq.num_asq_entries + * - hw->aq.arq_buf_size + * + * Do *NOT* hold the lock when calling this as the memory allocation routines + * called are not going to be atomic context safe + **/ +enum i40e_status_code i40e_init_asq(struct i40e_hw *hw) +{ + enum i40e_status_code ret_code = I40E_SUCCESS; + + if (hw->aq.asq.count > 0) { + /* queue already initialized */ + ret_code = I40E_ERR_NOT_READY; + goto init_adminq_exit; + } + + /* verify input for valid configuration */ + if ((hw->aq.num_asq_entries == 0) || + (hw->aq.asq_buf_size == 0)) { + ret_code = I40E_ERR_CONFIG; + goto init_adminq_exit; + } + + hw->aq.asq.next_to_use = 0; + hw->aq.asq.next_to_clean = 0; + hw->aq.asq.count = hw->aq.num_asq_entries; + + /* allocate the ring memory */ + ret_code = i40e_alloc_adminq_asq_ring(hw); + if (ret_code != I40E_SUCCESS) + goto init_adminq_exit; + + /* allocate buffers in the rings */ + ret_code = i40e_alloc_asq_bufs(hw); + if (ret_code != I40E_SUCCESS) + goto init_adminq_free_rings; + + /* initialize base registers */ + ret_code = i40e_config_asq_regs(hw); + if (ret_code != I40E_SUCCESS) + goto init_adminq_free_rings; + + /* success! */ + goto init_adminq_exit; + +init_adminq_free_rings: + i40e_free_adminq_asq(hw); + +init_adminq_exit: + return ret_code; +} + +/** + * i40e_init_arq - initialize ARQ + * @hw: pointer to the hardware structure + * + * The main initialization routine for the Admin Receive (Event) Queue. + * Prior to calling this function, drivers *MUST* set the following fields + * in the hw->aq structure: + * - hw->aq.num_asq_entries + * - hw->aq.arq_buf_size + * + * Do *NOT* hold the lock when calling this as the memory allocation routines + * called are not going to be atomic context safe + **/ +enum i40e_status_code i40e_init_arq(struct i40e_hw *hw) +{ + enum i40e_status_code ret_code = I40E_SUCCESS; + + if (hw->aq.arq.count > 0) { + /* queue already initialized */ + ret_code = I40E_ERR_NOT_READY; + goto init_adminq_exit; + } + + /* verify input for valid configuration */ + if ((hw->aq.num_arq_entries == 0) || + (hw->aq.arq_buf_size == 0)) { + ret_code = I40E_ERR_CONFIG; + goto init_adminq_exit; + } + + hw->aq.arq.next_to_use = 0; + hw->aq.arq.next_to_clean = 0; + hw->aq.arq.count = hw->aq.num_arq_entries; + + /* allocate the ring memory */ + ret_code = i40e_alloc_adminq_arq_ring(hw); + if (ret_code != I40E_SUCCESS) + goto init_adminq_exit; + *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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