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Date:      Tue, 15 Nov 2016 21:29:25 +0000 (GMT)
From:      jenkins-admin@FreeBSD.org
To:        jhb@FreeBSD.org, markj@FreeBSD.org, loos@FreeBSD.org, alc@FreeBSD.org,  mizhka@FreeBSD.org, jenkins-admin@FreeBSD.org, freebsd-current@FreeBSD.org
Subject:   FreeBSD_HEAD_amd64_gcc - Build #1704 - Fixed
Message-ID:  <619932747.39.1479245429559.JavaMail.jenkins@jenkins-9.freebsd.org>
In-Reply-To: <640877052.37.1479218950230.JavaMail.jenkins@jenkins-9.freebsd.org>
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FreeBSD_HEAD_amd64_gcc - Build #1704 - Fixed:

Build information: https://jenkins.FreeBSD.org/job/FreeBSD_HEAD_amd64_gcc/1704/
Full change log: https://jenkins.FreeBSD.org/job/FreeBSD_HEAD_amd64_gcc/1704/changes
Full build log: https://jenkins.FreeBSD.org/job/FreeBSD_HEAD_amd64_gcc/1704/console

Change summaries:

308695 by mizhka:
[BHND] correct spelling error in macro name

This commit is part of D6920 review. One of macro had wrong prefix:
 BMCA => BCMA

Reviewed by:	landonf, adrian (mentor)
Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D6920

308694 by markj:
Plug a lock leak in sysctl_ifmalist().

Fix style in the local variable declarations.

PR:		214542
MFC after:	1 week

308693 by loos:
Change the TI aintc driver name to "ti_aintc" to avoid the conflict with
the aintc driver for Allwinner A10.

This fixes the boot of the GENERIC ARM kernel on TI/AM335x SoCs.

Sponsored by:	Rubicon Communications, LLC (Netgate)

308692 by loos:
Fix ti_gpio_detach() to avoid crashing if something goes wrong.

Sponsored by:	Rubicon Communication, LLC (Netgate)

308691 by alc:
Remove most of the code for implementing PG_CACHED pages.  (This change does
not remove user-space visible fields from vm_cnt or all of the references to
cached pages from comments.  Those changes will come later.)

Reviewed by:	kib, markj
Tested by:	pho
Sponsored by:	Dell EMC Isilon
Differential Revision:	https://reviews.freebsd.org/D8497

308690 by jhb:
Sync instruction cache's after writing user breakpoints on MIPS.

Add an implementation for pmaps_sync_icache() on MIPS that sync's the
instruction cache on all CPUs via smp_rendezvous() after a debugger
inserts a breakpoint via ptrace(PT_IO).

Tested by:	kan (on Creator CI20 running Ingenic JZ4780 SOC)
MFC after:	2 weeks
Sponsored by:	DARPA / AFRL




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