Date: Tue, 13 Jan 2015 11:52:00 -0800 From: Sean Bruno <sbruno@ignoranthack.me> To: freebsd-mips@freebsd.org Subject: Re: [RFC] Cache control from user land (patch) Message-ID: <54B57760.3090508@ignoranthack.me> In-Reply-To: <1421175994697-5980362.post@n5.nabble.com> References: <1421175994697-5980362.post@n5.nabble.com>
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 On 01/13/15 11:06, sson wrote: > Hi all: > > Below is a link to a patch that provides a sysarch() so that cache > lines may be invalidated from userspace (via the sysarch() system > call). For convenience mips_cacheflush() is provided in the > machine/cachectl.h header file: > > int mips_cacheflush(void *addr, size_t nbytes, int whichcache); > > mips_cacheflush() flushes the content of the selected cache for the > user addresses in the range from addr to (addr+nbytes-1). > whichcache may be: > > MIPS_CF_ICACHE: Flush the instruction cache lines for a given > user address range. MIPS_CF_DCACHE: Write back to memory and > invalidate the cache lines for a given user address range. > MIPS_CF_BCACHE: Write back and invalidate both types of caches for > a given user address range. MIPS_CF_ICACHE_ALL, MIPS_CF_DCACHE, or > MIPS_CF_BCACHE: Full the entire given cache(s). > > mips_cacheflush() may return the errno EFAULT or EINVAL (whichcache > is not valid). In short, it is similar to the cacheflush() that > netbsd provides for mips. > > The diff: > https://people.freebsd.org/~sson/mips/cacheflush/mips_cacheflush.diff > > Comments, concerns, questions, suggestions, etc. are welcome. > > Regards, > > -stacey. > > > > I've tried applying this to head. I get a reject from the last bits to sys/mips/mips/sys_machdep.c % cat sys/mips/mips/sys_machdep.c.rej.orig @@ -39,6 +39,8 @@ #include <sys/syscall.h> #include <sys/sysent.h> +#include <machine/cache.h> +#include <machine/cachectl.h> #include <machine/cpufunc.h> #include <machine/cpuinfo.h> #include <machine/sysarch.h> @@ -63,9 +115,6 @@ * update it as well. Add the TLS and TCB offsets so the * value in this register is adjusted like in the case of the * rdhwr trap() instruction handler. - - * - - * XXXSS For more information why this offset is required see: - - * 'git show c6be4f4d2d1b71c04de5d3bbb6933ce2dbcdb317' */ if (cpuinfo.userlocal_reg == true) { #if defined(__mips_n64) && defined(COMPAT_FREEBSD32) @@ -94,6 +143,8 @@ case CHERI_SET_STACK: return (cheri_sysarch_setstack(td, uap)); #endif + case MIPS_CACHEFLUSH: + return (mips_sysarch_cacheflush(td, uap)); default: break; -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQF8BAEBCgBmBQJUtXddXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25zLm9w ZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCQUFENDYzMkU3MTIxREU4RDIwOTk3REQx MjAxRUZDQTFFNzI3RTY0AAoJEBIB78oecn5kzVEH/jpRQeaRNybEv5C7PFiHU0pd NgT6ebfEddNd61P9HqxC3NVQ4US8h5uFRewQWJ/hiXXUsfj3iGvNS2QgaX1SgU16 lXgTEu6IrgfIImtn87cMjXUblGySF1yhh/vMdBkdF4WWqgcUcaWrbr8vibGj6DD9 k4dRKDTci2c6eHNWQbA6pwyqdtDoQit4jMwT+ayjxckkGCx37DLZy7VrzhzmE5YB EO+QcUqjGRNHxmhtkil5eNBlrXeJT+FetlY/l4/4G2OATTYGbsdK78s91dhSlwZ2 umma95WWs+wfi23wZf4xm96DpV7dhh8PvaNJhw4MKldyll4lDIWwuYI+LaqjSPo= =b/5h -----END PGP SIGNATURE-----
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