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Date:      Sun, 13 Oct 2002 04:11:11 -0700
From:      Terry Lambert <tlambert2@mindspring.com>
To:        ticso@cicely.de
Cc:        "M. Warner Losh" <imp@bsdimp.com>, hch@infradead.org, wes@softweyr.com, dillon@apollo.backplane.com, vova@sw.ru, nate@root.org, arch@FreeBSD.org
Subject:   Re: Database indexes and ram
Message-ID:  <3DA954CF.98B0891A@mindspring.com>
References:  <200210082051.g98KpjU1084793@apollo.backplane.com> <3DA4C271.37AACAA3@softweyr.com> <20021012135245.A16453@infradead.org> <20021012.150616.129769790.imp@bsdimp.com> <20021013103538.GG17920@cicely8.cicely.de>

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Bernd Walter wrote:
> > : Umm, Linux _does_ DMA into any memory if the NIC/HBA/whatever supports
> > : it.
> >
> > Unless the card is 64bit, it can't DMA past 4G.
> 
> Shouldn't all modern pci chips support two 32bit word addresses.

Maybe.  The issue is the connectors.  That you can use 64 bit chips
in nominally 32 bit cards actually makes the situation much worse:
if we could tell 64 bit vs. 32 bit data path all the way to the DMA
engine on the card (without needing to trigger a DMA and have
a mirror area in physical memory both above and below the 32 bit
mark, to see where the data actually goes), then it would be much
less of a problem.

In most cases, the DMA gets put directly into memory mapped by the
VM of the kernel (the KVA).  FreeBSD has a unified VM and buffer
cache.  It makes little to no sense to DMA directly into user space
from hardware; among other things, it means that protection would
be limited to page boundaries, and you would break cache coherency
between mmap() and read/write I/O to files for which the DMA'ed data
was the backing store.  In effect, this means that all DMA'ed data
has to be known to the kernel.

I would be interested in knowing how Linux "knows" that the DMA
target for a card, with a driver which has communicated a 64 bit
DMA target address to it, has been modified, and how it deals with
shared memory segments, mmap'ed data, and data that needs to be
kept coherent between processes with different PAE/PSE-36 mappings
(i.e. process P1 and P2, where P2 has memory below 4G, and P2 has
memory above 8G, so the mappings do not coincide in a region of
physical memory shared by both processes -- or that's even *possible*
to have coresident in the KVA at the same time).

-- Terry

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