Date: Sat, 19 Sep 2020 10:06:19 +0000 (UTC) From: =?UTF-8?Q?Stefan_E=c3=9fer?= <se@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r548953 - head/lang/silq Message-ID: <202009191006.08JA6JxV071988@repo.freebsd.org>
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Author: se Date: Sat Sep 19 10:06:19 2020 New Revision: 548953 URL: https://svnweb.freebsd.org/changeset/ports/548953 Log: Update to latest github version This update includes an example of Shor's algorithm and otheer new examples. Modified: head/lang/silq/Makefile head/lang/silq/distinfo head/lang/silq/pkg-plist Modified: head/lang/silq/Makefile ============================================================================== --- head/lang/silq/Makefile Sat Sep 19 09:36:54 2020 (r548952) +++ head/lang/silq/Makefile Sat Sep 19 10:06:19 2020 (r548953) @@ -1,11 +1,11 @@ # $FreeBSD$ PORTNAME= silq -PORTVERSION= 20200621 +PORTVERSION= 20200919 CATEGORIES= lang math science MAINTAINER= se@FreeBSD.org -COMMENT= Silq from ETH Zürich +COMMENT= Silq from ETH Zürich LICENSE= BSL LICENSE_FILE= ${WRKSRC}/LICENSE @@ -17,9 +17,9 @@ BUILD_DEPENDS= ldmd2:lang/ldc USE_GITHUB= yes -GH_TUPLE= eth-sri:silq:7331c54 \ - tgehr:ast:3018b4b:ast/ast \ - tgehr:util:27168af:util/util +GH_TUPLE= eth-sri:silq:b09da8a \ + tgehr:ast:0e36dc2:ast/ast \ + tgehr:util:eb42377:util/util OPTIONS_DEFINE= EXAMPLES Modified: head/lang/silq/distinfo ============================================================================== --- head/lang/silq/distinfo Sat Sep 19 09:36:54 2020 (r548952) +++ head/lang/silq/distinfo Sat Sep 19 10:06:19 2020 (r548953) @@ -1,7 +1,7 @@ -TIMESTAMP = 1592756190 -SHA256 (eth-sri-silq-20200621-7331c54_GH0.tar.gz) = 3cc9869bb6902b09004c45a3e73ada272df8b0f03dcff03fd89e0c7d1bf25893 -SIZE (eth-sri-silq-20200621-7331c54_GH0.tar.gz) = 265843 -SHA256 (tgehr-ast-3018b4b_GH0.tar.gz) = 9328b7adf58a7077745c89f6bafa403bf0f9bb8f96468f2f035a1dced88c5eae -SIZE (tgehr-ast-3018b4b_GH0.tar.gz) = 72267 -SHA256 (tgehr-util-27168af_GH0.tar.gz) = 78363e2ec4942698f66c798fff03ac652ed30173fc8759369709032295aa221a -SIZE (tgehr-util-27168af_GH0.tar.gz) = 9449 +TIMESTAMP = 1600509579 +SHA256 (eth-sri-silq-20200621-b09da8a_GH0.tar.gz) = eebe522f281a8fbf4b8fbba0d4e08e914e5fbbb49d4351111d923b8af3861008 +SIZE (eth-sri-silq-20200621-b09da8a_GH0.tar.gz) = 239729 +SHA256 (tgehr-ast-0e36dc2_GH0.tar.gz) = a5639c2ba0851790363231bc02b6aab52e198b0916038ed3a8b7a763561632ae +SIZE (tgehr-ast-0e36dc2_GH0.tar.gz) = 73136 +SHA256 (tgehr-util-eb42377_GH0.tar.gz) = 52dee367fb158d604cf80dff8b576adf61de0c34d7f0d4f9548f403049602ddd +SIZE (tgehr-util-eb42377_GH0.tar.gz) = 9457 Modified: head/lang/silq/pkg-plist ============================================================================== --- head/lang/silq/pkg-plist Sat Sep 19 09:36:54 2020 (r548952) +++ head/lang/silq/pkg-plist Sat Sep 19 10:06:19 2020 (r548953) @@ -6,6 +6,7 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/asinQ.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/asinQ2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/assertTypeError.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignFromArray.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignQcontrol.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignQuantumArray.slq @@ -114,6 +115,7 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/conditionalMeasurement2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/constBlockAssign.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/constBlockCapture.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumeDepTypeVar.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumingVector.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/conv.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertForget.slq @@ -136,6 +138,8 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/distinguishStates.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/divbyzero.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/divbyzero2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/divmod.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/dlog.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/dump.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/dump2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/dumpExit.slq @@ -152,6 +156,8 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/earlyReturn7.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/earlyReturn8.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/earlyReturnQuantumIf.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/extendTruncate.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/extendTruncateError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/fib.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/fib2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/flipAll.slq @@ -208,6 +214,7 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/intUintBoolConversion.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/integerPhase.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/invQ.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/invalidConstAnnotationError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/invalidReturnTypeInference.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite2.slq @@ -217,6 +224,7 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/lengthMismatch.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/liftedAssign.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/liftedConstArg.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/localVariableInFunctionReturnTypeError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/majorityOracle.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/makeWPower2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/map1.slq @@ -234,6 +242,9 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed4.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed5.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiForget.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiIndex1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiIndex2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiIndex3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiReplace.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiResultIndexReplace.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedClosure.slq @@ -243,6 +254,7 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/newForLoopRangeSyntax.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/noImplicitForget.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/opAssignReverse.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/paramNotConsumedError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/parameterizedSimulation.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/parseArrayOfVectorReturn.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/parseError.slq @@ -312,6 +324,7 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseX.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/shadowCaptured.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/shadowing.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/shor.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/sinQ.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/singletonVectorHadamard.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/specialReverseTypeChecking.slq @@ -326,16 +339,19 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapEmptyIf.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapInt.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapVarWithComponent.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/teleportation.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/test.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/test3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/test3_2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/test3_3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/test3_4.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/test3_5.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testBadTypeAnnotation.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testForget.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testGenericConvert1.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testGenericConvert2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testHadamard.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testLiftedClassical.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testParamSameName.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testQFT.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testQFT2.slq @@ -350,19 +366,26 @@ bin/silq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testReverse2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testReverse3.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/testReverse4.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst1.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst2.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst3.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst4.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/thirds.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/transpose.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/tupleArray.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/tupleConversion.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeAlias.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeConstBlockCapture.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeError2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeFunCall.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeFunCallCoerce.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/uncomputeOnArrayAssignment.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/unicodeLoc.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/unrealizableError.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorConv.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorToArray.slq +%%PORTEXAMPLES%%%%EXAMPLESDIR%%/warning.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/while.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/while2.slq %%PORTEXAMPLES%%%%EXAMPLESDIR%%/whileFunctionCall.slq
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