Date: Fri, 17 Oct 2014 06:23:05 +0000 (UTC) From: Neel Natu <neel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r273207 - in projects/bhyve_svm: sys/amd64/vmm sys/x86/include usr.sbin/bhyve Message-ID: <201410170623.s9H6N5Ph044049@svn.freebsd.org>
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Author: neel Date: Fri Oct 17 06:23:04 2014 New Revision: 273207 URL: https://svnweb.freebsd.org/changeset/base/273207 Log: Don't advertise the Instruction Based Sampling feature because it requires emulating a large number of MSRs. Ignore writes to a couple more AMD-specific MSRs and return 0 on read. This further reduces the unimplemented MSRs accessed by a Linux guest on boot. Modified: projects/bhyve_svm/sys/amd64/vmm/x86.c projects/bhyve_svm/sys/x86/include/specialreg.h projects/bhyve_svm/usr.sbin/bhyve/xmsr.c Modified: projects/bhyve_svm/sys/amd64/vmm/x86.c ============================================================================== --- projects/bhyve_svm/sys/amd64/vmm/x86.c Fri Oct 17 04:36:53 2014 (r273206) +++ projects/bhyve_svm/sys/amd64/vmm/x86.c Fri Oct 17 06:23:04 2014 (r273207) @@ -167,6 +167,11 @@ x86_emulate_cpuid(struct vm *vm, int vcp regs[2] &= ~AMDID2_PTSCEL2I; /* + * Don't advertise Instruction Based Sampling feature. + */ + regs[2] &= ~AMDID2_IBS; + + /* * Hide rdtscp/ia32_tsc_aux until we know how * to deal with them. */ Modified: projects/bhyve_svm/sys/x86/include/specialreg.h ============================================================================== --- projects/bhyve_svm/sys/x86/include/specialreg.h Fri Oct 17 04:36:53 2014 (r273206) +++ projects/bhyve_svm/sys/x86/include/specialreg.h Fri Oct 17 06:23:04 2014 (r273207) @@ -784,6 +784,8 @@ #define MSR_IORRMASK1 0xc0010019 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ +#define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ +#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ #define MSR_MC0_CTL_MASK 0xc0010044 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ Modified: projects/bhyve_svm/usr.sbin/bhyve/xmsr.c ============================================================================== --- projects/bhyve_svm/usr.sbin/bhyve/xmsr.c Fri Oct 17 04:36:53 2014 (r273206) +++ projects/bhyve_svm/usr.sbin/bhyve/xmsr.c Fri Oct 17 06:23:04 2014 (r273207) @@ -69,6 +69,10 @@ emulate_wrmsr(struct vmctx *ctx, int vcp */ return (0); + case MSR_NB_CFG1: + case MSR_IC_CFG: + return (0); /* Ignore writes */ + case MSR_PERFEVSEL0: case MSR_PERFEVSEL1: case MSR_PERFEVSEL2: @@ -127,6 +131,15 @@ emulate_rdmsr(struct vmctx *ctx, int vcp *val |= 1 << 9; /* MONITOR/MWAIT disable */ break; + case MSR_NB_CFG1: + case MSR_IC_CFG: + /* + * The reset value is processor family dependent so + * just return 0. + */ + *val = 0; + break; + case MSR_PERFEVSEL0: case MSR_PERFEVSEL1: case MSR_PERFEVSEL2:
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