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Date:      Mon, 14 Dec 1998 14:31:42 +0100
From:      "Martin Husemann" <martin@rumolt.teuto.de>
To:        "Martin Recktenwald" <mreckt@wurzelausix.CS.Uni-SB.DE>, "Gerald Heinig" <heinig@hdz-ima.rwth-aachen.de>
Cc:        <freebsd-isdn@FreeBSD.ORG>
Subject:   RE: ISAC & HSCX questions
Message-ID:  <000001be2766$164cec40$53cb08d4@hwart.teuto.de>
In-Reply-To: <wtz7lvvufa3.fsf@wurzelausix.cs.uni-sb.de>

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> Maybe because you can write at the FIFO where you want but it will
> alway store the bytes in the order you wrote them?

This is a typical hardware designer game: the chip (internaly) has a
receive-FIFO and a transmit-FIFO. They are fifos, as the chip always places
bytes at one end of the receive fifo and you always read the first-in byte
from the other end. Same for the write access to the transmit fifo (only the
other way around).

Now: to minimize the address decoding part of the chip they overlapped both
fifos: all read accesses go to the receive fifo, all write acceses to the
transmit fifo (from that point of view the R/W signal is just another
address bit).

Now for the driver writer: to optimize the access you'll like to use a
"string" opcode, like on the i386 "iosb", which does multiple transfers from
the same port to a buffer. Whith some luck you can read a full fifo content
by one instruction.

Unfortunately some architectures don't have io-ports but instead use
memory-mapped io. The same architectures often don't have an 'iosb'
aequivalent (see the 68000 family). To play the same 'single instruction
full fifo fetch' trick there the hardware designers chose to ignore the
lower address bits when accessing the fifo: you code a memory block
transfer, just like in C "memcpy(dest_buffer, rx_fifo, 32);", which can be
done with autoincrement addressing modes on the 68000.

Many modern cards use this feature to reduce the size of the mapped io area
of the card: they split access to the chipset in two steps: first you write
the address of the register you would like to access to an address latch
register, then you access one data register. You'll need a minimum of two
io-ports (four to eight used on real-world cards) for such a card, which
suits well into the ISA-PnP world. And the "iosb" trick still works: just
write the fifo address once into the latch, then do "iosb" on the data port.


Martin


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