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Date:      Wed, 9 Apr 1997 13:02:00 +0200
From:      Stefan Esser <se@freebsd.org>
To:        stesin@gu.net
Cc:        hackers@freebsd.org, scsi@freebsd.org
Subject:   Re: 2 PCI busses, 2 AIC chips, 2.2.1. Howto ?
Message-ID:  <19970409130200.12143@x14.mi.uni-koeln.de>
In-Reply-To: <Pine.BSF.3.95q.970402122302.283F-100000@trifork.gu.net>; from Andrew Stesin on Wed, Apr 02, 1997 at 01:03:25PM %2B0300
References:  <Pine.BSF.3.95q.970402122302.283F-100000@trifork.gu.net>

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On Apr 2, Andrew Stesin <stesin@gu.net> wrote:

Sorry for the late reply, I just returned from a vacation ...

> The box: Intel XXpress-<smth>, 2 AIC7870 chips onboard, EISA bus present.

Is this a Pentium or PPro system ?

> neither of AICs are recognized at boot. ??? I have the following guesses:
> 
> 1. neither of the 2 SCSI busses has anything attached yet (disk drives will
>    come in a day or two, they ordered drives separately, and no Wide
>    drives here to try).

Should not cause any trouble ...

> 3. 2.2.1 has some problem with two PCI busses? (while both AICs are
>    on the second bus??? or on EISA???) What I see at boot
>    after the "Probing devices on the pci:0 bus" message:
> 
> chip0 <generic PCI bridge (vendor=8086 device=1225 subclass=0)> \
> 	rev 2 on pci0:0
> chip1 <Intel 82375EB PCI-EISA bridge> rev 5 on pci0:14
> pci0:15:0: Intel Corporation device=0x0008, class=0xff, subclass=0x00 \
> 	[no driver assigned]
> .....^^^^....
> 	This last message is repeated exactly for all pci0:15:[0-7]
> 	values.

This may be caused by (incorrectly) assuming, that chip
was a multi-function device. This does not cause any 
problems, though ...

> What I am missing?  Any comments and explanations are appreciated!

Seems you have some way of obtaining the boot message log.
Could you please provide me with VERBOSE boot messages ?
(Eenter "-v" at the "Boot: " prompt.)

The problem you are facing comes from the fact, that PCI 
specifies a single bus directly attached to the CPU, and
a tree structure of seconfary buses connected to it.
Since this limits the number of low-latency slots to at
most 5, server machines often come with more than one bus
directly attached to the CPU. But there is no standard way
of telling, how many buses are actually connected to a CPU
(1 is assumed), and while the bus numbers behing PCI to PCI
bridges can be determined in a chip-independent way, this
is not possible in the case of multiple CPU to PCI chips.
Device specific code has to be added for each of them.

(The information on the number of buses can be queried by 
calling the PCI BIOS, but I'd prefer, if I not have to,
for a number of reasons ...)

I need more information on the chip set used on that mother
board. The Orion should be supported out of the box, but if
this is a system with multiple PCI buses directly attached
to the CPU based on some other chip set, a small addition 
to the PCI probe code will be required.

Regards, STefan



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