Date: Mon, 15 Apr 2013 18:30:01 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r249518 - stable/9/contrib/llvm/lib/Support Message-ID: <201304151830.r3FIU1Hd023205@svn.freebsd.org>
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Author: dim Date: Mon Apr 15 18:30:00 2013 New Revision: 249518 URL: http://svnweb.freebsd.org/changeset/base/249518 Log: Pull in r178636 from upstream llvm trunk: Second pass at addressing PR15351 by explicitly checking for AVX support when getting the host processor information. It emits a .byte sequence on GNUC compilers to work around lack of xgetbv support with older assemblers, and resolves a comment typo found in the previous patch. This should fix crashes due to emitting of AVX instructions on certain processors, which do not support then, when using -march=native. This is a direct commit to stable/9, since head has a complete import of llvm/clang trunk, and there is no single commit to merge. Reported by: Kubilay Kocak <koobs.freebsd@gmail.com> Modified: stable/9/contrib/llvm/lib/Support/Host.cpp Modified: stable/9/contrib/llvm/lib/Support/Host.cpp ============================================================================== --- stable/9/contrib/llvm/lib/Support/Host.cpp Mon Apr 15 17:59:06 2013 (r249517) +++ stable/9/contrib/llvm/lib/Support/Host.cpp Mon Apr 15 18:30:00 2013 (r249518) @@ -111,6 +111,21 @@ static bool GetX86CpuIDAndInfo(unsigned #endif } +static bool OSHasAVXSupport() { +#if defined( __GNUC__ ) + // Check xgetbv; this uses a .byte sequence instead of the instruction + // directly because older assemblers do not include support for xgetbv and + // there is no easy way to conditionally compile based on the assembler used. + int rEAX, rEDX; + __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); +#elif defined(_MSC_VER) + unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); +#else + int rEAX = 0; // Ensures we return false +#endif + return (rEAX & 6) == 6; +} + static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) { Family = (EAX >> 8) & 0xf; // Bits 8 - 11 @@ -133,6 +148,10 @@ std::string sys::getHostCPUName() { DetectX86FamilyModel(EAX, Family, Model); bool HasSSE3 = (ECX & 0x1); + // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV + // indicates that the AVX registers will be saved and restored on context + // switch, then we have full AVX support. + bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport(); GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); bool Em64T = (EDX >> 29) & 0x1; @@ -242,11 +261,15 @@ std::string sys::getHostCPUName() { case 42: // Intel Core i7 processor. All processors are manufactured // using the 32 nm process. case 45: - return "corei7-avx"; + // Not all Sandy Bridge processors support AVX (such as the Pentium + // versions instead of the i7 versions). + return HasAVX ? "corei7-avx" : "corei7"; // Ivy Bridge: case 58: - return "core-avx-i"; + // Not all Ivy Bridge processors support AVX (such as the Pentium + // versions instead of the i7 versions). + return HasAVX ? "core-avx-i" : "corei7"; case 28: // Most 45 nm Intel Atom processors case 38: // 45 nm Atom Lincroft
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