Date: Sun, 18 Oct 2015 19:54:11 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r289537 - in head/sys/arm: conf freescale/imx Message-ID: <201510181954.t9IJsBKJ086917@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: ian Date: Sun Oct 18 19:54:11 2015 New Revision: 289537 URL: https://svnweb.freebsd.org/changeset/base/289537 Log: Enable ARM_INTRNG on IMX6 platforms, and make the imx_gpio driver an interrupt controller. The latter is required for INTRNG, because of the hardware erratum workaround installed by the linux folks into the imx6 FDT data, which remaps an ethernet interrupt to the gpio device. In the non-INTRNG world we intercept the call to map the interrupt and map it back to the ethernet hardware (because we don't need linux's workaround), but in the INTRNG world we lose the hookpoint where that remapping was happening, but we gain the ability to work the way linux does by having the gpio driver dispatch the interrupt. Modified: head/sys/arm/conf/IMX6 head/sys/arm/freescale/imx/imx6_machdep.c head/sys/arm/freescale/imx/imx_gpio.c Modified: head/sys/arm/conf/IMX6 ============================================================================== --- head/sys/arm/conf/IMX6 Sun Oct 18 19:05:56 2015 (r289536) +++ head/sys/arm/conf/IMX6 Sun Oct 18 19:54:11 2015 (r289537) @@ -22,6 +22,8 @@ ident IMX6 include "std.armv6" include "../freescale/imx/std.imx6" +options ARM_INTRNG + options SOC_IMX6 options HZ=500 # Scheduling quantum is 2 milliseconds. Modified: head/sys/arm/freescale/imx/imx6_machdep.c ============================================================================== --- head/sys/arm/freescale/imx/imx6_machdep.c Sun Oct 18 19:05:56 2015 (r289536) +++ head/sys/arm/freescale/imx/imx6_machdep.c Sun Oct 18 19:54:11 2015 (r289537) @@ -58,6 +58,7 @@ struct fdt_fixup_entry fdt_fixup_table[] static uint32_t gpio1_node; +#ifndef ARM_INTRNG /* * Work around the linux workaround for imx6 erratum 006687, in which some * ethernet interrupts don't go to the GPC and thus won't wake the system from @@ -91,6 +92,7 @@ fdt_pic_decode_t fdt_pic_table[] = { &imx6_decode_fdt, NULL }; +#endif static vm_offset_t imx6_lastaddr(platform_t plat) Modified: head/sys/arm/freescale/imx/imx_gpio.c ============================================================================== --- head/sys/arm/freescale/imx/imx_gpio.c Sun Oct 18 19:05:56 2015 (r289536) +++ head/sys/arm/freescale/imx/imx_gpio.c Sun Oct 18 19:54:11 2015 (r289537) @@ -34,6 +34,8 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); +#include "opt_platform.h" + #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> @@ -44,8 +46,10 @@ __FBSDID("$FreeBSD$"); #include <sys/lock.h> #include <sys/mutex.h> #include <sys/gpio.h> +#include <sys/proc.h> #include <machine/bus.h> +#include <machine/intr.h> #include <machine/resource.h> #include <dev/fdt/fdt_common.h> @@ -56,13 +60,9 @@ __FBSDID("$FreeBSD$"); #include "gpio_if.h" -#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) -#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) -#define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->sc_mtx, \ - device_get_nameunit(_sc->sc_dev), "imx_gpio", MTX_DEF) -#define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); -#define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); -#define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); +#ifdef ARM_INTRNG +#include "pic_if.h" +#endif #define WRITE4(_sc, _r, _v) \ bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) @@ -95,13 +95,13 @@ struct imx51_gpio_softc { device_t dev; device_t sc_busdev; struct mtx sc_mtx; - struct resource *sc_res[11]; /* 1 x mem, 2 x IRQ, 8 x IRQ */ - void *gpio_ih[11]; /* 1 ptr is not a big waste */ - int sc_l_irq; /* Last irq resource */ + struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */ + void *gpio_ih[2]; bus_space_tag_t sc_iot; bus_space_handle_t sc_ioh; int gpio_npins; struct gpio_pin gpio_pins[NGPIO]; + struct arm_irqsrc *gpio_pic_irqsrc[NGPIO]; }; static struct ofw_compat_data compat_data[] = { @@ -118,18 +118,6 @@ static struct resource_spec imx_gpio_spe { -1, 0 } }; -static struct resource_spec imx_gpio0irq_spec[] = { - { SYS_RES_IRQ, 2, RF_ACTIVE }, - { SYS_RES_IRQ, 3, RF_ACTIVE }, - { SYS_RES_IRQ, 4, RF_ACTIVE }, - { SYS_RES_IRQ, 5, RF_ACTIVE }, - { SYS_RES_IRQ, 6, RF_ACTIVE }, - { SYS_RES_IRQ, 7, RF_ACTIVE }, - { SYS_RES_IRQ, 8, RF_ACTIVE }, - { SYS_RES_IRQ, 9, RF_ACTIVE }, - { -1, 0 } -}; - /* * Helpers */ @@ -142,7 +130,6 @@ static void imx51_gpio_pin_configure(str static int imx51_gpio_probe(device_t); static int imx51_gpio_attach(device_t); static int imx51_gpio_detach(device_t); -static int imx51_gpio_intr(void *); /* * GPIO interface @@ -157,12 +144,258 @@ static int imx51_gpio_pin_set(device_t, static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *); static int imx51_gpio_pin_toggle(device_t, uint32_t pin); +#ifdef ARM_INTRNG +/* + * this is teardown_intr + */ +static void +gpio_pic_disable_intr(device_t dev, struct arm_irqsrc *isrc) +{ + struct imx51_gpio_softc *sc; + u_int irq; + + sc = device_get_softc(dev); + irq = isrc->isrc_data; + + // XXX Not sure this is necessary + mtx_lock_spin(&sc->sc_mtx); + CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); + WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); + mtx_unlock_spin(&sc->sc_mtx); +} + +/* + * this is mask_intr + */ +static void +gpio_pic_disable_source(device_t dev, struct arm_irqsrc *isrc) +{ + struct imx51_gpio_softc *sc; + + sc = device_get_softc(dev); + + mtx_lock_spin(&sc->sc_mtx); + CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << isrc->isrc_data)); + mtx_unlock_spin(&sc->sc_mtx); +} + +/* + * this is setup_intr + */ +static void +gpio_pic_enable_intr(device_t dev, struct arm_irqsrc *isrc) +{ + struct imx51_gpio_softc *sc; + int icfg; + u_int irq, reg, shift, wrk; + + sc = device_get_softc(dev); + + if (isrc->isrc_trig == INTR_TRIGGER_LEVEL) { + if (isrc->isrc_pol == INTR_POLARITY_LOW) + icfg = GPIO_ICR_COND_LOW; + else + icfg = GPIO_ICR_COND_HIGH; + } else { + if (isrc->isrc_pol == INTR_POLARITY_HIGH) + icfg = GPIO_ICR_COND_FALL; + else + icfg = GPIO_ICR_COND_RISE; + } + + irq = isrc->isrc_data; + if (irq < 16) { + reg = IMX_GPIO_ICR1_REG; + shift = 2 * irq; + } else { + reg = IMX_GPIO_ICR2_REG; + shift = 2 * (irq - 16); + } + + mtx_lock_spin(&sc->sc_mtx); + CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); + WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); + wrk = READ4(sc, reg); + wrk &= ~(0x03 << shift); + wrk |= icfg << shift; + WRITE4(sc, reg, wrk); + mtx_unlock_spin(&sc->sc_mtx); +} + +/* + * this is unmask_intr + */ +static void +gpio_pic_enable_source(device_t dev, struct arm_irqsrc *isrc) +{ + struct imx51_gpio_softc *sc; + + sc = device_get_softc(dev); + + mtx_lock_spin(&sc->sc_mtx); + SET4(sc, IMX_GPIO_IMR_REG, (1U << isrc->isrc_data)); + mtx_unlock_spin(&sc->sc_mtx); +} + +static void +gpio_pic_post_filter(device_t dev, struct arm_irqsrc *isrc) +{ + struct imx51_gpio_softc *sc; + + sc = device_get_softc(dev); + + arm_irq_memory_barrier(0); + /* EOI. W1C reg so no r-m-w, no locking needed. */ + WRITE4(sc, IMX_GPIO_ISR_REG, (1U << isrc->isrc_data)); +} + +static void +gpio_pic_post_ithread(device_t dev, struct arm_irqsrc *isrc) +{ + + arm_irq_memory_barrier(0); + gpio_pic_enable_source(dev, isrc); +} + +static void +gpio_pic_pre_ithread(device_t dev, struct arm_irqsrc *isrc) +{ + + gpio_pic_disable_source(dev, isrc); +} + +/* + * intrng calls this to make a new isrc known to us. + */ +static int +gpio_pic_register(device_t dev, struct arm_irqsrc *isrc, boolean_t *is_percpu) +{ + struct imx51_gpio_softc *sc; + u_int irq, tripol; + + sc = device_get_softc(dev); + + /* + * From devicetree/bindings/gpio/fsl-imx-gpio.txt: + * #interrupt-cells: 2. The first cell is the GPIO number. The second + * cell bits[3:0] is used to specify trigger type and level flags: + * 1 = low-to-high edge triggered. + * 2 = high-to-low edge triggered. + * 4 = active high level-sensitive. + * 8 = active low level-sensitive. + * We can do any single one of these modes, but nothing in combo. + */ + + if (isrc->isrc_ncells != 2) { + device_printf(sc->dev, "Invalid #interrupt-cells"); + return (EINVAL); + } + + irq = isrc->isrc_cells[0]; + tripol = isrc->isrc_cells[1]; + if (irq >= sc->gpio_npins) { + device_printf(sc->dev, "Invalid interrupt number %d", irq); + return (EINVAL); + } + switch (tripol) + { + case 1: + isrc->isrc_trig = INTR_TRIGGER_EDGE; + isrc->isrc_pol = INTR_POLARITY_HIGH; + break; + case 2: + isrc->isrc_trig = INTR_TRIGGER_EDGE; + isrc->isrc_pol = INTR_POLARITY_LOW; + break; + case 4: + isrc->isrc_trig = INTR_TRIGGER_LEVEL; + isrc->isrc_pol = INTR_POLARITY_HIGH; + break; + case 8: + isrc->isrc_trig = INTR_TRIGGER_LEVEL; + isrc->isrc_pol = INTR_POLARITY_LOW; + break; + default: + device_printf(sc->dev, "unsupported trigger/polarity 0x%2x\n", + tripol); + return (ENOTSUP); + } + isrc->isrc_nspc_type = ARM_IRQ_NSPC_PLAIN; + isrc->isrc_nspc_num = irq; + + /* + * 1. The link between ISRC and controller must be set atomically. + * 2. Just do things only once in rare case when consumers + * of shared interrupt came here at the same moment. + */ + mtx_lock_spin(&sc->sc_mtx); + if (sc->gpio_pic_irqsrc[irq] != NULL) { + mtx_unlock_spin(&sc->sc_mtx); + return (sc->gpio_pic_irqsrc[irq] == isrc ? 0 : EEXIST); + } + sc->gpio_pic_irqsrc[irq] = isrc; + isrc->isrc_data = irq; + mtx_unlock_spin(&sc->sc_mtx); + + arm_irq_set_name(isrc, "%s,%u", device_get_nameunit(sc->dev), irq); + return (0); +} + +static int +gpio_pic_unregister(device_t dev, struct arm_irqsrc *isrc) +{ + struct imx51_gpio_softc *sc; + u_int irq; + + sc = device_get_softc(dev); + + mtx_lock_spin(&sc->sc_mtx); + irq = isrc->isrc_data; + if (sc->gpio_pic_irqsrc[irq] != isrc) { + mtx_unlock_spin(&sc->sc_mtx); + return (sc->gpio_pic_irqsrc[irq] == NULL ? 0 : EINVAL); + } + sc->gpio_pic_irqsrc[irq] = NULL; + isrc->isrc_data = 0; + mtx_unlock_spin(&sc->sc_mtx); + + arm_irq_set_name(isrc, ""); + return (0); +} + +static int +gpio_pic_filter(void *arg) +{ + struct imx51_gpio_softc *sc; + uint32_t i, interrupts; + + sc = arg; + mtx_lock_spin(&sc->sc_mtx); + interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG); + mtx_unlock_spin(&sc->sc_mtx); + + for (i = 0; interrupts != 0; i++, interrupts >>= 1) { + if ((interrupts & 0x1) == 0) + continue; + if (sc->gpio_pic_irqsrc[i]) + arm_irq_dispatch(sc->gpio_pic_irqsrc[i], curthread->td_intr_frame); + else + device_printf(sc->dev, "spurious interrupt %d\n", i); + } + + return (FILTER_HANDLED); +} +#endif + +/* + * + */ static void imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin, unsigned int flags) { - GPIO_LOCK(sc); + mtx_lock_spin(&sc->sc_mtx); /* * Manage input/output @@ -171,15 +404,15 @@ imx51_gpio_pin_configure(struct imx51_gp pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); if (flags & GPIO_PIN_OUTPUT) { pin->gp_flags |= GPIO_PIN_OUTPUT; - SET4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin)); + SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); } else { pin->gp_flags |= GPIO_PIN_INPUT; - CLEAR4(sc, IMX_GPIO_OE_REG, (1 << pin->gp_pin)); + CLEAR4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); } } - GPIO_UNLOCK(sc); + mtx_unlock_spin(&sc->sc_mtx); } static device_t @@ -195,8 +428,11 @@ imx51_gpio_get_bus(device_t dev) static int imx51_gpio_pin_max(device_t dev, int *maxpin) { + struct imx51_gpio_softc *sc; + + sc = device_get_softc(dev); + *maxpin = sc->gpio_npins - 1; - *maxpin = NGPIO - 1; return (0); } @@ -215,9 +451,9 @@ imx51_gpio_pin_getcaps(device_t dev, uin if (i >= sc->gpio_npins) return (EINVAL); - GPIO_LOCK(sc); + mtx_lock_spin(&sc->sc_mtx); *caps = sc->gpio_pins[i].gp_caps; - GPIO_UNLOCK(sc); + mtx_unlock_spin(&sc->sc_mtx); return (0); } @@ -237,9 +473,9 @@ imx51_gpio_pin_getflags(device_t dev, ui if (i >= sc->gpio_npins) return (EINVAL); - GPIO_LOCK(sc); + mtx_lock_spin(&sc->sc_mtx); *flags = sc->gpio_pins[i].gp_flags; - GPIO_UNLOCK(sc); + mtx_unlock_spin(&sc->sc_mtx); return (0); } @@ -259,9 +495,9 @@ imx51_gpio_pin_getname(device_t dev, uin if (i >= sc->gpio_npins) return (EINVAL); - GPIO_LOCK(sc); + mtx_lock_spin(&sc->sc_mtx); memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME); - GPIO_UNLOCK(sc); + mtx_unlock_spin(&sc->sc_mtx); return (0); } @@ -301,12 +537,12 @@ imx51_gpio_pin_set(device_t dev, uint32_ if (i >= sc->gpio_npins) return (EINVAL); - GPIO_LOCK(sc); + mtx_lock_spin(&sc->sc_mtx); if (value) - SET4(sc, IMX_GPIO_DR_REG, (1 << i)); + SET4(sc, IMX_GPIO_DR_REG, (1U << i)); else - CLEAR4(sc, IMX_GPIO_DR_REG, (1 << i)); - GPIO_UNLOCK(sc); + CLEAR4(sc, IMX_GPIO_DR_REG, (1U << i)); + mtx_unlock_spin(&sc->sc_mtx); return (0); } @@ -326,9 +562,9 @@ imx51_gpio_pin_get(device_t dev, uint32_ if (i >= sc->gpio_npins) return (EINVAL); - GPIO_LOCK(sc); + mtx_lock_spin(&sc->sc_mtx); *val = (READ4(sc, IMX_GPIO_DR_REG) >> i) & 1; - GPIO_UNLOCK(sc); + mtx_unlock_spin(&sc->sc_mtx); return (0); } @@ -348,35 +584,15 @@ imx51_gpio_pin_toggle(device_t dev, uint if (i >= sc->gpio_npins) return (EINVAL); - GPIO_LOCK(sc); + mtx_lock_spin(&sc->sc_mtx); WRITE4(sc, IMX_GPIO_DR_REG, - (READ4(sc, IMX_GPIO_DR_REG) ^ (1 << i))); - GPIO_UNLOCK(sc); + (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << i))); + mtx_unlock_spin(&sc->sc_mtx); return (0); } static int -imx51_gpio_intr(void *arg) -{ - struct imx51_gpio_softc *sc; - uint32_t input, value; - - sc = arg; - input = READ4(sc, IMX_GPIO_ISR_REG); - value = input & READ4(sc, IMX_GPIO_IMR_REG); - WRITE4(sc, IMX_GPIO_ISR_REG, input); - - if (!value) - goto intr_done; - - /* TODO: interrupt handling */ - -intr_done: - return (FILTER_HANDLED); -} - -static int imx51_gpio_probe(device_t dev) { @@ -395,10 +611,13 @@ static int imx51_gpio_attach(device_t dev) { struct imx51_gpio_softc *sc; - int i, irq; + int i, irq, unit; sc = device_get_softc(dev); - mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); + sc->dev = dev; + sc->gpio_npins = NGPIO; + + mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), NULL, MTX_SPIN); if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) { device_printf(dev, "could not allocate resources\n"); @@ -407,40 +626,40 @@ imx51_gpio_attach(device_t dev) return (ENXIO); } - sc->dev = dev; - sc->gpio_npins = NGPIO; - sc->sc_l_irq = 2; sc->sc_iot = rman_get_bustag(sc->sc_res[0]); sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]); - - if (bus_alloc_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]) == 0) { - /* - * First GPIO unit able to serve +8 interrupts for 8 first - * pins. - */ - sc->sc_l_irq = 10; - } - - for (irq = 1; irq <= sc->sc_l_irq; irq ++) { - if ((bus_setup_intr(dev, sc->sc_res[irq], INTR_TYPE_MISC, - imx51_gpio_intr, NULL, sc, &sc->gpio_ih[irq]))) { + /* + * Mask off all interrupts in hardware, then set up interrupt handling. + */ + WRITE4(sc, IMX_GPIO_IMR_REG, 0); + for (irq = 0; irq < 2; irq++) { +#ifdef ARM_INTRNG + if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK, + gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) { device_printf(dev, "WARNING: unable to register interrupt handler\n"); imx51_gpio_detach(dev); return (ENXIO); } +#endif } + unit = device_get_unit(dev); for (i = 0; i < sc->gpio_npins; i++) { sc->gpio_pins[i].gp_pin = i; sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; sc->gpio_pins[i].gp_flags = - (READ4(sc, IMX_GPIO_OE_REG) & (1 << i)) ? GPIO_PIN_OUTPUT: + (READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, - "imx_gpio%d.%d", device_get_unit(dev), i); + "imx_gpio%d.%d", unit, i); } + +#ifdef ARM_INTRNG + arm_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev))); +#endif sc->sc_busdev = gpiobus_attach_bus(dev); + if (sc->sc_busdev == NULL) { imx51_gpio_detach(dev); return (ENXIO); @@ -457,14 +676,11 @@ imx51_gpio_detach(device_t dev) sc = device_get_softc(dev); - KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); - gpiobus_detach_bus(dev); - for (irq = 1; irq <= sc->sc_l_irq; irq ++) { + for (irq = 1; irq <= 2; irq++) { if (sc->gpio_ih[irq]) bus_teardown_intr(dev, sc->sc_res[irq], sc->gpio_ih[irq]); } - bus_release_resources(dev, imx_gpio0irq_spec, &sc->sc_res[3]); bus_release_resources(dev, imx_gpio_spec, sc->sc_res); mtx_destroy(&sc->sc_mtx); @@ -476,6 +692,19 @@ static device_method_t imx51_gpio_method DEVMETHOD(device_attach, imx51_gpio_attach), DEVMETHOD(device_detach, imx51_gpio_detach), +#ifdef ARM_INTRNG + /* Interrupt controller interface */ + DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr), + DEVMETHOD(pic_disable_source, gpio_pic_disable_source), + DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr), + DEVMETHOD(pic_enable_source, gpio_pic_enable_source), + DEVMETHOD(pic_post_filter, gpio_pic_post_filter), + DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread), + DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread), + DEVMETHOD(pic_register, gpio_pic_register), + DEVMETHOD(pic_unregister, gpio_pic_unregister), +#endif + /* GPIO protocol */ DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus), DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max),
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201510181954.t9IJsBKJ086917>