From owner-p4-projects@FreeBSD.ORG Tue Nov 25 18:29:13 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id DDF5D1065678; Tue, 25 Nov 2008 18:29:12 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A076F1065672 for ; Tue, 25 Nov 2008 18:29:12 +0000 (UTC) (envelope-from sam@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 94E958FC16 for ; Tue, 25 Nov 2008 18:29:12 +0000 (UTC) (envelope-from sam@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id mAPITCqh095286 for ; Tue, 25 Nov 2008 18:29:12 GMT (envelope-from sam@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id mAPITCLB095284 for perforce@freebsd.org; Tue, 25 Nov 2008 18:29:12 GMT (envelope-from sam@freebsd.org) Date: Tue, 25 Nov 2008 18:29:12 GMT Message-Id: <200811251829.mAPITCLB095284@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to sam@freebsd.org using -f From: Sam Leffler To: Perforce Change Reviews Cc: Subject: PERFORCE change 153540 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Nov 2008 18:29:13 -0000 http://perforce.freebsd.org/chv.cgi?CH=153540 Change 153540 by sam@sam_ebb on 2008/11/25 18:28:20 Overhaul to eliminate hardwired assumptions about memory layout; in particular the assumption we inherited from netbsd that memory is aliased at 0x10000000. With these changes we now reliably boot with PHYSADDR 0 on both Avila and Cambria boards. Affected files ... .. //depot/projects/vap/sys/arm/xscale/ixp425/avila_machdep.c#8 edit Differences ... ==== //depot/projects/vap/sys/arm/xscale/ixp425/avila_machdep.c#8 (text+ko) ==== @@ -95,6 +95,11 @@ #include #include +/* kernel text starts where we were loaded at boot */ +#define KERNEL_TEXT_OFF (KERNPHYSADDR - PHYSADDR) +#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF) +#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF) + #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ #define KERNEL_PT_IO 1 #define KERNEL_PT_IO_NUM 3 @@ -248,6 +253,8 @@ void * initarm(void *arg, void *arg2) { +#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1)) +#define next_page(a) next_chunk2(a,PAGE_SIZE) struct pv_addr kernel_l1pt; int loop, i; u_int l1pagetable; @@ -263,20 +270,35 @@ pcpu_init(pcpup, 0, sizeof(struct pcpu)); PCPU_SET(curthread, &thread0); - freemempos = 0x10200000; - /* Define a macro to simplify memory allocation */ -#define valloc_pages(var, np) \ - alloc_pages((var).pv_pa, (np)); \ - (var).pv_va = (var).pv_pa + 0xb0000000; + /* + * We allocate memory downwards from where we were loaded + * by RedBoot; first the L1 page table, then NUM_KERNEL_PTS + * entries in the L2 page table. Past that we re-align the + * allocation boundary so later data structures (stacks, etc) + * can be mapped with different attributes (write-back vs + * write-through). Note this leaves a gap for expansion + * (or might be repurposed). + */ + freemempos = KERNPHYSADDR; -#define alloc_pages(var, np) \ - freemempos -= (np * PAGE_SIZE); \ - (var) = freemempos; \ - memset((char *)(var), 0, ((np) * PAGE_SIZE)); + /* macros to simplify initial memory allocation */ +#define alloc_pages(var, np) do { \ + freemempos -= (np * PAGE_SIZE); \ + (var) = freemempos; \ + /* NB: this works because locore maps PA=VA */ \ + memset((char *)(var), 0, ((np) * PAGE_SIZE)); \ +} while (0) +#define valloc_pages(var, np) do { \ + alloc_pages((var).pv_pa, (np)); \ + (var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); \ +} while (0) + /* force L1 page table alignment */ while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) freemempos -= PAGE_SIZE; + /* allocate contiguous L1 page table */ valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); + /* now allocate L2 page tables; they are linked to L1 below */ for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { valloc_pages(kernel_pt_table[loop], @@ -286,11 +308,18 @@ (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * L2_TABLE_SIZE_REAL; kernel_pt_table[loop].pv_va = - kernel_pt_table[loop].pv_pa + 0xb0000000; + kernel_pt_table[loop].pv_pa + + (KERNVIRTADDR - KERNPHYSADDR); } } - freemem_pt = freemempos; - freemempos = 0x10100000; + freemem_pt = freemempos; /* base of allocated pt's */ + + /* + * Re-align allocation boundary so we can map there area + * write-back instead of write-through for the stacks and + * related structures allocated below. + */ + freemempos = PHYSADDR + 0x100000; /* * Allocate a page for the system page mapped to V0x00000000 * This page will just contain the system vectors and can be @@ -306,30 +335,25 @@ alloc_pages(minidataclean.pv_pa, 1); valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE); #ifdef ARM_USE_SMALL_ALLOC +#error "I am broken" /* XXX save people grief */ freemempos -= PAGE_SIZE; freemem_pt = trunc_page(freemem_pt); freemem_after = freemempos - ((freemem_pt - 0x10100000) / PAGE_SIZE) * sizeof(struct arm_small_page); - arm_add_smallalloc_pages((void *)(freemem_after + 0xb0000000) + arm_add_smallalloc_pages((void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR) , (void *)0xc0100000, freemem_pt - 0x10100000, 1); freemem_after -= ((freemem_after - 0x10001000) / PAGE_SIZE) * sizeof(struct arm_small_page); - arm_add_smallalloc_pages((void *)(freemem_after + 0xb0000000) + arm_add_smallalloc_pages((void *)(freemem_after + (KEYVIRTADDR - KERNPHYSADDR)) , (void *)0xc0001000, trunc_page(freemem_after) - 0x10001000, 0); freemempos = trunc_page(freemem_after); freemempos -= PAGE_SIZE; #endif - /* - * Allocate memory for the l1 and l2 page tables. The scheme to avoid - * wasting memory by allocating the l1pt on the first 16k memory was - * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for - * this to work (which is supposed to be the case). - */ /* - * Now we start construction of the L1 page table - * We start by mapping the L2 page tables into the L1. - * This means that we can replace L1 mappings later on if necessary + * Now construct the L1 page table. First map the L2 + * page tables into the L1 so we can replace L1 mappings + * later on if necessary */ l1pagetable = kernel_l1pt.pv_va; @@ -348,19 +372,17 @@ VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000, 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); - pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, PHYSADDR + 0x200000, - (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1), + pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS, + next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE), VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1); - afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - - 1)); + freemem_after = next_page((int)lastaddr); + afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE)); for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); } pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - #ifdef ARM_USE_SMALL_ALLOC if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) { @@ -390,6 +412,7 @@ setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); + /* * Pages were allocated during the secondary bootstrap for the * stacks for different CPU modes. @@ -398,17 +421,10 @@ * Since the ARM stacks use STMFD etc. we must set r13 to the top end * of the stack memory. */ - - - set_stackptr(PSR_IRQ32_MODE, - irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); - set_stackptr(PSR_ABT32_MODE, - abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); - set_stackptr(PSR_UND32_MODE, - undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); + set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE*PAGE_SIZE); + set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE*PAGE_SIZE); + set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE*PAGE_SIZE); - - /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any @@ -429,12 +445,12 @@ physmem = memsize / PAGE_SIZE; /* Set stack for exception handlers */ - + data_abort_handler_address = (u_int)data_abort_handler; prefetch_abort_handler_address = (u_int)prefetch_abort_handler; undefined_handler_address = (u_int)undefinedinstruction_bounce; undefined_init(); - + proc_linkup0(&proc0, &thread0); thread0.td_kstack = kernelstack.pv_va; thread0.td_pcb = (struct pcb *) @@ -442,25 +458,20 @@ thread0.td_pcb->pcb_flags = 0; thread0.td_frame = &proc0_tf; pcpup->pc_curpcb = thread0.td_pcb; - - /* Enable MMU, I-cache, D-cache, write buffer. */ arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); - - pmap_curmaxkvaddr = afterkern + PAGE_SIZE; dump_avail[0] = PHYSADDR; dump_avail[1] = PHYSADDR + memsize; dump_avail[2] = 0; dump_avail[3] = 0; - - pmap_bootstrap(pmap_curmaxkvaddr, - 0xd0000000, &kernel_l1pt); + + pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, MSGBUF_SIZE); mutex_init(); - + i = 0; #ifdef ARM_USE_SMALL_ALLOC phys_avail[i++] = PHYSADDR; @@ -473,7 +484,7 @@ phys_avail[i++] = trunc_page(PHYSADDR + memsize - 1); phys_avail[i++] = 0; phys_avail[i] = 0; - + /* Do basic tuning, hz etc */ init_param1(); init_param2(physmem); @@ -485,4 +496,6 @@ return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - sizeof(struct pcb))); +#undef next_page +#undef next_chunk2 }