Date: Mon, 23 May 2011 21:11:46 +0000 (UTC) From: Pyun YongHyeon <yongari@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r222227 - head/sys/dev/msk Message-ID: <201105232111.p4NLBkaB037981@svn.freebsd.org>
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Author: yongari Date: Mon May 23 21:11:46 2011 New Revision: 222227 URL: http://svn.freebsd.org/changeset/base/222227 Log: Do not touch ASF related register for controllers that do not have these registers. Also disable Watchdog of ASF microcontroller. Modified: head/sys/dev/msk/if_msk.c head/sys/dev/msk/if_mskreg.h Modified: head/sys/dev/msk/if_msk.c ============================================================================== --- head/sys/dev/msk/if_msk.c Mon May 23 21:00:56 2011 (r222226) +++ head/sys/dev/msk/if_msk.c Mon May 23 21:11:46 2011 (r222227) @@ -1296,23 +1296,30 @@ mskc_reset(struct msk_softc *sc) int i, initram; /* Disable ASF. */ - if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { - status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); - /* Clear AHB bridge & microcontroller reset. */ - status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | - Y2_ASF_HCU_CCSR_CPU_RST_MODE); - /* Clear ASF microcontroller state. */ - status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK; - CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); - } else - CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); - CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); - - /* - * Since we disabled ASF, S/W reset is required for Power Management. - */ - CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); - CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); + if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && + sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { + if (sc->msk_hw_id == CHIP_ID_YUKON_EX || + sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { + CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); + status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); + /* Clear AHB bridge & microcontroller reset. */ + status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | + Y2_ASF_HCU_CCSR_CPU_RST_MODE); + /* Clear ASF microcontroller state. */ + status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; + status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; + CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); + CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); + } else + CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); + CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); + /* + * Since we disabled ASF, S/W reset is required for + * Power Management. + */ + CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); + CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); + } /* Clear all error bits in the PCI status register. */ status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); Modified: head/sys/dev/msk/if_mskreg.h ============================================================================== --- head/sys/dev/msk/if_mskreg.h Mon May 23 21:00:56 2011 (r222226) +++ head/sys/dev/msk/if_mskreg.h Mon May 23 21:11:46 2011 (r222227) @@ -677,6 +677,7 @@ /* ASF Subsystem Registers (Yukon-2 only) */ #define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ #define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ +#define B28_Y2_CPU_WDOG 0x0e48 /* 32 bit Watchdog Register */ #define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ #define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ #define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */
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