Date: Tue, 4 May 2010 10:14:06 +0000 (UTC) From: Kevin Lo <kevlo@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r207611 - in head/sys: arm/arm arm/include conf Message-ID: <201005041014.o44AE6A6076880@svn.freebsd.org>
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Author: kevlo Date: Tue May 4 10:14:05 2010 New Revision: 207611 URL: http://svn.freebsd.org/changeset/base/207611 Log: Add support for FA626TE. Tested on GM8181 development board. Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/arm/cpufunc_asm_fa526.S head/sys/arm/arm/elf_trampoline.c head/sys/arm/arm/identcpu.c head/sys/arm/include/cpuconf.h head/sys/arm/include/cpufunc.h head/sys/conf/options.arm Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Tue May 4 08:37:28 2010 (r207610) +++ head/sys/arm/arm/cpufunc.c Tue May 4 10:14:05 2010 (r207611) @@ -783,69 +783,66 @@ struct cpu_functions xscalec3_cpufuncs = #endif /* CPU_XSCALE_81342 */ -#if defined(CPU_FA526) +#if defined(CPU_FA526) || defined(CPU_FA626TE) struct cpu_functions fa526_cpufuncs = { /* CPU functions */ - .cf_id = cpufunc_id, - .cf_cpwait = cpufunc_nullop, + cpufunc_id, /* id */ + cpufunc_nullop, /* cpwait */ /* MMU functions */ - .cf_control = cpufunc_control, - .cf_domains = cpufunc_domains, - .cf_setttb = fa526_setttb, - .cf_faultstatus = cpufunc_faultstatus, - .cf_faultaddress = cpufunc_faultaddress, + cpufunc_control, /* control */ + cpufunc_domains, /* domain */ + fa526_setttb, /* setttb */ + cpufunc_faultstatus, /* faultstatus */ + cpufunc_faultaddress, /* faultaddress */ /* TLB functions */ - .cf_tlb_flushID = armv4_tlb_flushID, - .cf_tlb_flushID_SE = fa526_tlb_flushID_SE, - .cf_tlb_flushI = armv4_tlb_flushI, - .cf_tlb_flushI_SE = fa526_tlb_flushI_SE, - .cf_tlb_flushD = armv4_tlb_flushD, - .cf_tlb_flushD_SE = armv4_tlb_flushD_SE, + armv4_tlb_flushID, /* tlb_flushID */ + fa526_tlb_flushID_SE, /* tlb_flushID_SE */ + armv4_tlb_flushI, /* tlb_flushI */ + fa526_tlb_flushI_SE, /* tlb_flushI_SE */ + armv4_tlb_flushD, /* tlb_flushD */ + armv4_tlb_flushD_SE, /* tlb_flushD_SE */ /* Cache operations */ - .cf_icache_sync_all = fa526_icache_sync_all, - .cf_icache_sync_range = fa526_icache_sync_range, - - .cf_dcache_wbinv_all = fa526_dcache_wbinv_all, - .cf_dcache_wbinv_range = fa526_dcache_wbinv_range, - .cf_dcache_inv_range = fa526_dcache_inv_range, - .cf_dcache_wb_range = fa526_dcache_wb_range, - - .cf_idcache_wbinv_all = fa526_idcache_wbinv_all, - .cf_idcache_wbinv_range = fa526_idcache_wbinv_range, - - - .cf_l2cache_wbinv_all = cpufunc_nullop, - .cf_l2cache_wbinv_range = (void *)cpufunc_nullop, - .cf_l2cache_inv_range = (void *)cpufunc_nullop, - .cf_l2cache_wb_range = (void *)cpufunc_nullop, + fa526_icache_sync_all, /* icache_sync_all */ + fa526_icache_sync_range, /* icache_sync_range */ + fa526_dcache_wbinv_all, /* dcache_wbinv_all */ + fa526_dcache_wbinv_range, /* dcache_wbinv_range */ + fa526_dcache_inv_range, /* dcache_inv_range */ + fa526_dcache_wb_range, /* dcache_wb_range */ + + fa526_idcache_wbinv_all, /* idcache_wbinv_all */ + fa526_idcache_wbinv_range, /* idcache_wbinv_range */ + cpufunc_nullop, /* l2cache_wbinv_all */ + (void *)cpufunc_nullop, /* l2cache_wbinv_range */ + (void *)cpufunc_nullop, /* l2cache_inv_range */ + (void *)cpufunc_nullop, /* l2cache_wb_range */ /* Other functions */ - .cf_flush_prefetchbuf = fa526_flush_prefetchbuf, - .cf_drain_writebuf = armv4_drain_writebuf, - .cf_flush_brnchtgt_C = cpufunc_nullop, - .cf_flush_brnchtgt_E = fa526_flush_brnchtgt_E, + fa526_flush_prefetchbuf, /* flush_prefetchbuf */ + armv4_drain_writebuf, /* drain_writebuf */ + cpufunc_nullop, /* flush_brnchtgt_C */ + fa526_flush_brnchtgt_E, /* flush_brnchtgt_E */ - .cf_sleep = fa526_cpu_sleep, + fa526_cpu_sleep, /* sleep */ /* Soft functions */ - .cf_dataabt_fixup = cpufunc_null_fixup, - .cf_prefetchabt_fixup = cpufunc_null_fixup, + cpufunc_null_fixup, /* dataabt_fixup */ + cpufunc_null_fixup, /* prefetchabt_fixup */ - .cf_context_switch = fa526_context_switch, + fa526_context_switch, /* context_switch */ - .cf_setup = fa526_setup -}; -#endif /* CPU_FA526 */ + fa526_setup /* cpu setup */ +}; +#endif /* CPU_FA526 || CPU_FA626TE */ /* @@ -856,11 +853,11 @@ struct cpu_functions cpufuncs; u_int cputype; u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */ -#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ - defined (CPU_ARM9E) || defined (CPU_ARM10) || \ - defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ - defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_FA526) || \ +#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ + defined (CPU_ARM9E) || defined (CPU_ARM10) || \ + defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ + defined(CPU_FA526) || defined(CPU_FA626TE) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) static void get_cachetype_cp15(void); @@ -1141,8 +1138,8 @@ set_cpufuncs() goto out; } #endif /* CPU_SA1110 */ -#ifdef CPU_FA526 - if (cputype == CPU_ID_FA526) { +#if defined(CPU_FA526) || defined(CPU_FA626TE) + if (cputype == CPU_ID_FA526 || cputype == CPU_ID_FA626TE) { cpufuncs = fa526_cpufuncs; cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */ get_cachetype_cp15(); @@ -1153,7 +1150,7 @@ set_cpufuncs() goto out; } -#endif /* CPU_FA526 */ +#endif /* CPU_FA526 || CPU_FA626TE */ #ifdef CPU_IXP12X0 if (cputype == CPU_ID_IXP1200) { cpufuncs = ixp12x0_cpufuncs; @@ -1629,7 +1626,7 @@ late_abort_fixup(arg) defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ defined(CPU_ARM10) || defined(CPU_ARM11) || \ - defined(CPU_FA526) + defined(CPU_FA526) || defined(CPU_FA626TE) #define IGN 0 #define OR 1 @@ -2095,7 +2092,7 @@ sa11x0_setup(args) } #endif /* CPU_SA1100 || CPU_SA1110 */ -#if defined(CPU_FA526) +#if defined(CPU_FA526) || defined(CPU_FA626TE) struct cpu_option fa526_options[] = { #ifdef COMPAT_12 { "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE | @@ -2149,7 +2146,7 @@ fa526_setup(char *args) ctrl = cpuctrl; cpu_control(0xffffffff, cpuctrl); } -#endif /* CPU_FA526 */ +#endif /* CPU_FA526 || CPU_FA626TE */ #if defined(CPU_IXP12X0) Modified: head/sys/arm/arm/cpufunc_asm_fa526.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_fa526.S Tue May 4 08:37:28 2010 (r207610) +++ head/sys/arm/arm/cpufunc_asm_fa526.S Tue May 4 10:14:05 2010 (r207611) @@ -32,7 +32,11 @@ #include <machine/asm.h> __FBSDID("$FreeBSD$"); +#ifdef CPU_FA526 #define CACHELINE_SIZE 16 +#else +#define CACHELINE_SIZE 32 +#endif ENTRY(fa526_setttb) mov r1, #0 Modified: head/sys/arm/arm/elf_trampoline.c ============================================================================== --- head/sys/arm/arm/elf_trampoline.c Tue May 4 08:37:28 2010 (r207610) +++ head/sys/arm/arm/elf_trampoline.c Tue May 4 10:14:05 2010 (r207611) @@ -57,7 +57,7 @@ void __startC(void); #define cpu_idcache_wbinv_all arm8_cache_purgeID #elif defined(CPU_ARM9) #define cpu_idcache_wbinv_all arm9_idcache_wbinv_all -#elif defined(CPU_FA526) +#elif defined(CPU_FA526) || defined(CPU_FA626TE) #define cpu_idcache_wbinv_all fa526_idcache_wbinv_all #elif defined(CPU_ARM9E) #define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all Modified: head/sys/arm/arm/identcpu.c ============================================================================== --- head/sys/arm/arm/identcpu.c Tue May 4 08:37:28 2010 (r207610) +++ head/sys/arm/arm/identcpu.c Tue May 4 10:14:05 2010 (r207611) @@ -220,7 +220,9 @@ const struct cpuidtab cpuids[] = { generic_steppings }, { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", generic_steppings }, - { CPU_ID_FA526, CPU_CLASS_ARM9, "FA526", + { CPU_ID_FA526, CPU_CLASS_ARM9, "FA526", + generic_steppings }, + { CPU_ID_FA626TE, CPU_CLASS_ARM9ES, "FA626TE", generic_steppings }, { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", Modified: head/sys/arm/include/cpuconf.h ============================================================================== --- head/sys/arm/include/cpuconf.h Tue May 4 08:37:28 2010 (r207610) +++ head/sys/arm/include/cpuconf.h Tue May 4 10:14:05 2010 (r207611) @@ -62,6 +62,7 @@ defined(CPU_XSCALE_80321) + \ defined(CPU_XSCALE_PXA2X0) + \ defined(CPU_FA526) + \ + defined(CPU_FA626TE) + \ defined(CPU_XSCALE_IXP425)) /* @@ -78,7 +79,7 @@ #if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ - defined(CPU_XSCALE_PXA2X0)) + defined(CPU_XSCALE_PXA2X0) || defined(CPU_FA626TE)) #define ARM_ARCH_5 1 #else #define ARM_ARCH_5 0 @@ -126,7 +127,8 @@ #if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ - defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_FA526)) + defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_FA526) || \ + defined(CPU_FA626TE)) #define ARM_MMU_GENERIC 1 #else #define ARM_MMU_GENERIC 0 Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Tue May 4 08:37:28 2010 (r207610) +++ head/sys/arm/include/cpufunc.h Tue May 4 10:14:05 2010 (r207611) @@ -284,7 +284,7 @@ u_int arm8_clock_config (u_int, u_int); #endif -#ifdef CPU_FA526 +#if defined(CPU_FA526) || defined(CPU_FA626TE) void fa526_setup (char *arg); void fa526_setttb (u_int ttb); void fa526_context_switch (void); @@ -464,11 +464,11 @@ extern unsigned armv5_dcache_index_max; extern unsigned armv5_dcache_index_inc; #endif -#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ - defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ - defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ - defined(CPU_FA526) || \ - defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ +#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ + defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ + defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_FA526) || defined(CPU_FA626TE) || \ + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) void armv4_tlb_flushID (void); Modified: head/sys/conf/options.arm ============================================================================== --- head/sys/conf/options.arm Tue May 4 08:37:28 2010 (r207610) +++ head/sys/conf/options.arm Tue May 4 10:14:05 2010 (r207611) @@ -37,3 +37,4 @@ AT91_BWCT opt_at91.h AT91_TSC opt_at91.h AT91_KWIKBYTE opt_at91.h CPU_FA526 opt_global.h +CPU_FA626TE opt_global.h
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