From owner-svn-src-head@FreeBSD.ORG Wed Nov 12 17:43:37 2008 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C409D1065678; Wed, 12 Nov 2008 17:43:37 +0000 (UTC) (envelope-from jkoshy@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id B8EEB8FC19; Wed, 12 Nov 2008 17:43:37 +0000 (UTC) (envelope-from jkoshy@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id mACHhbUt036589; Wed, 12 Nov 2008 17:43:37 GMT (envelope-from jkoshy@svn.freebsd.org) Received: (from jkoshy@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id mACHhbVb036586; Wed, 12 Nov 2008 17:43:37 GMT (envelope-from jkoshy@svn.freebsd.org) Message-Id: <200811121743.mACHhbVb036586@svn.freebsd.org> From: Joseph Koshy Date: Wed, 12 Nov 2008 17:43:37 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r184892 - head/lib/libpmc X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Nov 2008 17:43:37 -0000 Author: jkoshy Date: Wed Nov 12 17:43:37 2008 New Revision: 184892 URL: http://svn.freebsd.org/changeset/base/184892 Log: Document the alternate event names supported for "architectural" PMC events. Modified: head/lib/libpmc/pmc.atom.3 head/lib/libpmc/pmc.core.3 head/lib/libpmc/pmc.core2.3 Modified: head/lib/libpmc/pmc.atom.3 ============================================================================== --- head/lib/libpmc/pmc.atom.3 Wed Nov 12 17:38:23 2008 (r184891) +++ head/lib/libpmc/pmc.atom.3 Wed Nov 12 17:43:37 2008 (r184892) @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd September 24, 2008 +.Dd November 12, 2008 .Os .Dt PMC.ATOM 3 .Sh NAME @@ -273,13 +273,17 @@ The number of branch instructions decode The number of branches executed, but not necessarily retired. .It Li BR_INST_RETIRED.ANY .Pq Event C4H , Umask 00H +.Pq Alias Qq "Branch Instruction Retired" The number of branch instructions retired. +This is an architectural performance event. .It Li BR_INST_RETIRED.ANY1 .Pq Event C4H , Umask 0FH The number of branch instructions retired that were mispredicted. .It Li BR_INST_RETIRED.MISPRED .Pq Event C5, Umask 00H +.Pq Alias Qq "Branch Misses Retired" The number of mispredicted branch instructions retired. +This is an architectural performance event. .It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN .Pq Event C4H , Umask 02H The number of not taken branch instructions retired that were @@ -458,10 +462,14 @@ The number of times the L1 data cache is the same processor. .It Li CPU_CLK_UNHALTED.BUS .Pq Event 3CH , Umask 01H +.Pq Alias Qq "Unhalted Reference Cycles" The number of bus cycles when the core is not in the halt state. +This is an architectural performance event. .It Li CPU_CLK_UNHALTED.CORE_P .Pq Event 3CH , Umask 00H +.Pq Alias Qq "Unhalted Core Cycles" The number of core cycles while the core is not in a halt state. +This is an architectural performance event. .It Li CPU_CLK_UNHALTED.NO_OTHER .Pq Event 3CH , Umask 02H The number of bus cycles during which the core remains unhalted and @@ -597,7 +605,9 @@ length changing prefix. The number of cycles during which the instruction queue is full. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H +.Pq Alias Qq "Instruction Retired" The number of instructions retired. +This is an architectural performance event. .It Li INST_RETIRED.LOADS .Pq Event C0H , Umask 01H The number of instructions retired that contained a load operation. @@ -744,10 +754,13 @@ The number of L2 cache requests that wer The number of completed L2 cache requests. .It Li L2_RQSTS.SELF.DEMAND.I_STATE .Pq Event 2EH , Umask 41H +.Pq Alias Qq "LLC Misses" The number of completed L2 cache demand requests from this core that missed the L2 cache. +This is an architectural performance event. .It Li L2_RQSTS.SELF.DEMAND.MESI .Pq Event 2EH , Umask 4FH +.Pq Alias Qq "LLC References" The number of completed L2 cache demand requests from this core. .It Li L2_ST Xo .Op ,cachestate= Ns Ar state @@ -1154,16 +1167,15 @@ instructions retired. The following table shows the mapping between the PMC-independent aliases supported by .Lb libpmc -and the underlying hardware events used. -.Bl -column "branch-mispredicts" "Description" -.It Em Alias Ta Em Event -.It Li branches Ta Li BR_INST_RETIRED.ANY -.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED -.It Li dc-misses Ta Li L2_ST,core=this,cachestate=mesi -.It Li ic-misses Ta Li ICACHE.MISSES -.It Li instructions Ta Li INST_RETIRED.ANY_P -.It Li interrupts Ta Li HW_INT_RCV -.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P +and the underlying hardware events used on these CPUs. +.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class" +.It Em Alias Ta Em Event Ta Em PMC Class +.It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP +.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP +.It Li ic-misses Ta Li ICACHE.MISSES Ta Li PMC_CLASS_IAP +.It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF +.It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP +.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF .El .Sh SEE ALSO .Xr pmc 3 , Modified: head/lib/libpmc/pmc.core.3 ============================================================================== --- head/lib/libpmc/pmc.core.3 Wed Nov 12 17:38:23 2008 (r184891) +++ head/lib/libpmc/pmc.core.3 Wed Nov 12 17:43:37 2008 (r184892) @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd September 21, 2008 +.Dd November 12, 2008 .Os .Dt PMC.CORE 3 .Sh NAME @@ -234,11 +234,15 @@ The number of branch instructions execut .Pq Event E0H The number of branch instructions decoded. .It Li Br_Instr_Ret -.Pq Event C4H +.Pq Event C4H, Umask 00H +.Pq Alias Qq "Branch Instruction Retired" The number of branch instructions retired. +This is an architectural performance event. .It Li Br_MisPred_Ret -.Pq Event C5H +.Pq Event C5H, Umask 00H +.Pq Alias Qq "Branch Misses Retired" The number of mispredicted branch instructions retired. +This is an architectural performance event. .It Li Br_MisPred_Taken_Ret .Pq Event CAH The number of taken and mispredicted branches retired. @@ -475,7 +479,9 @@ The number of instruction TLB misses. The number of instructions decoded. .It Li Instr_Ret .Pq Event C0H +.Pq Alias Qq "Instruction Retired" The number of instructions retired. +This is an architectural performance event. .It Li L1_Pref_Req .Pq Event 4FH The number of L1 prefetch request due to data cache misses. @@ -546,6 +552,17 @@ The number of L2 cache writes including .It Li LD_Blocks .Pq Event 03H The number of load operations delayed due to store buffer blocks. +.It Li LLC_Misses +.Pq Event 2EH, Umask 41H +The number of cache misses for references to the last level cache, +excluding misses due to hardware prefetches. +This is an architectural performance event. +.It Li LLC_Reference +The number of references to the last level cache, +excluding those due to hardware prefetches. +This is an architectural performance event. +.Pq Event 2EH, Umask 4FH +This is an architectural performance event. .It Li MMX_Assist .Pq Event CDH The number of EMMX instructions executed. @@ -573,7 +590,9 @@ and integer multiplies. This event is available on PMC1 only. .It Li NonHlt_Ref_Cycles .Pq Event 3CH , Umask 01H +.Pq Alias Qq "Unhalted Reference Cycles" The number of non-halted bus cycles. +This is an architectural performance event. .It Li Pref_Rqsts_Dn .Pq Event F8H The number of hardware prefetch requests issued in backward streams. @@ -690,6 +709,11 @@ The duration in a thermal trip based on .It Li Unfusion .Pq Event DBH The number of unfusion events. +.It Li "Unhalted_Core_Cycles" +.Pq Event 3CH , Umask 00H +The number of core clock cycles when the clock signal on a specific +core is not halted. +This is an architectural performance event. .It Li Uops_Ret .Pq Event C2H The number of micro-ops retired. Modified: head/lib/libpmc/pmc.core2.3 ============================================================================== --- head/lib/libpmc/pmc.core2.3 Wed Nov 12 17:38:23 2008 (r184891) +++ head/lib/libpmc/pmc.core2.3 Wed Nov 12 17:43:37 2008 (r184892) @@ -23,7 +23,7 @@ .\" .\" $FreeBSD$ .\" -.Dd September 24, 2008 +.Dd November 12, 2008 .Os .Dt PMC.CORE2 3 .Sh NAME @@ -271,10 +271,14 @@ The number of branch instructions decode The number of branches executed, but not necessarily retired. .It Li BR_INST_RETIRED.ANY .Pq Event C4H , Umask 00H +.Pq Alias Qq "Branch Instruction Retired" The number of branch instructions retired. +This is an architectural performance event. .It Li BR_INST_RETIRED.MISPRED -.Pq Event C5H +.Pq Event C5H, Umask 00H +.Pq Alias Qq "Branch Misses Retired" The number of mispredicted branch instructions retired. +This is an architectural performance event. .It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN .Pq Event C4H , Umask 02H The number of not taken branch instructions retired that were @@ -446,10 +450,14 @@ The number of times the L1 data cache is the same processor. .It Li CPU_CLK_UNHALTED.BUS .Pq Event 3CH , Umask 01H +.Pq Alias Qq "Unhalted Reference Cycles" The number of bus cycles when the core is not in the halt state. +This is an architectural performance event. .It Li CPU_CLK_UNHALTED.CORE_P .Pq Event 3CH , Umask 00H +.Pq Alias Qq "Unhalted Core Cycles" The number of core cycles while the core is not in a halt state. +This is an architectural performance event. .It Li CPU_CLK_UNHALTED.NO_OTHER .Pq Event 3CH , Umask 02H The number of bus cycles during which the core remains unhalted and @@ -553,7 +561,9 @@ length changing prefix. The number of cycles during which the instruction queue is full. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H +.Pq Alias Qq "Instruction Retired" The number of instructions retired. +This is an architectural performance event. .It Li INST_RETIRED.LOADS .Pq Event C0H , Umask 01H The number of instructions retired that contained a load operation. @@ -705,11 +715,15 @@ The number of L2 cache requests that wer The number of completed L2 cache requests. .It Li L2_RQSTS.SELF.DEMAND.I_STATE .Pq Event 2EH , Umask 41H +.Pq Alias Qq "LLC Misses" The number of completed L2 cache demand requests from this core that missed the L2 cache. +This is an architectural performance event. .It Li L2_RQSTS.SELF.DEMAND.MESI .Pq Event 2EH , Umask 4FH +.Pq Alias Qq "LLC References" The number of completed L2 cache demand requests from this core. +This is an architectural performance event. .It Li L2_ST Xo .Op ,cachestate= Ns Ar state .Op ,core= Ns Ar core @@ -1075,15 +1089,14 @@ The following table shows the mapping be aliases supported by .Lb libpmc and the underlying hardware events used. -.Bl -column "branch-mispredicts" "Description" -.It Em Alias Ta Em Event -.It Li branches Ta Li BR_INST_RETIRED.ANY -.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED -.It Li dc-misses Ta Li L2_ST,core=this,cachestate=mesi -.It Li ic-misses Ta Li L1I_MISSES -.It Li instructions Ta Li INST_RETIRED.ANY_P -.It Li interrupts Ta Li HW_INT_RCV -.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P +.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class" +.It Em Alias Ta Em Event Ta Em PMC Class +.It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP +.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP +.It Li ic-misses Ta Li L1I_MISSES Ta Li PMC_CLASS_IAP +.It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF +.It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP +.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF .El .Sh SEE ALSO .Xr pmc 3 ,