Date: Wed, 16 Apr 2008 09:38:53 -0700 From: Marcel Moolenaar <xcllnt@mac.com> To: John Baldwin <jhb@freebsd.org> Cc: cvs-src@freebsd.org, src-committers@freebsd.org, cvs-all@freebsd.org Subject: Re: cvs commit: src/sys/ia64/ia64 sapic.c Message-ID: <46D21F70-BEC7-4627-97D4-1DE71D0BEAD2@mac.com> In-Reply-To: <200804160940.56271.jhb@freebsd.org> References: <200804142034.m3EKYjfs059229@repoman.freebsd.org> <200804160940.56271.jhb@freebsd.org>
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On Apr 16, 2008, at 6:40 AM, John Baldwin wrote: > On Monday 14 April 2008 04:34:45 pm Marcel Moolenaar wrote: >> marcel 2008-04-14 20:34:45 UTC >> >> FreeBSD src repository >> >> Modified files: >> sys/ia64/ia64 sapic.c >> Log: >> Revision 1.9 changes the delivery mode from the magic constant 0 >> (i.e. fixed delivery) to SAPIC_DELMODE_LOWPRI. While the commit >> log doesn't mention the change in behaviour, it is believed to be >> deliberate. In the last 5.5 years this hasn't been a problem. Nor >> do I think did it make any difference, but who knows. However, I >> do know that it break SMP support for Montecito-based machines. >> Switch back to fixed-CPU delivery so that SMP works again. This >> gives me some time to look more closely at the problem, as well >> as make sure the I-cache validation as it's implemented currently >> is sufficient in SMP configurations... > > Intel is deprecating the LOWPRI delivery mode on x86 CPUs with > x2APIC, so I > think it is probably best to switch to using FIXED mode on ia64 as > well (x86 > has used fixed mode since the new APIC code came in due to LOWPRI > being > effectively useless on P4 CPUs). That's good to know. If LOWPRI has the same destiny in Itanium chipsets as it has in Pentium chipsets, then I might as well avoid the hassle of getting it to work. Though, I do like it when all CPUs share in the interrupt handling. Maybe I can do that more easily with MSI (which I still need to implement :-) Thanks, -- Marcel Moolenaar xcllnt@mac.com
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