Date: Tue, 14 May 1996 11:29:59 -0500 (CDT) From: Joe Greco <jgreco@brasil.moneng.mei.com> To: davidg@root.com Cc: mmead@Glock.COM, joerg_wunsch@uriah.heep.sax.de, blh@nol.net, jgreco@brasil.moneng.mei.com, hackers@freebsd.org, hardware@freebsd.org Subject: Re: Triton chipset with 256k cache caches 32M only? Message-ID: <199605141630.LAA06612@brasil.moneng.mei.com> In-Reply-To: <199605141522.IAA12962@Root.COM> from "David Greenman" at May 14, 96 08:22:48 am
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> >> No, it uses the parity bits. Only 8 syndrome bits are needed > >> for 64bit words. > > > > Hmm. So does that mean the ECC is limited to single (odd > >number of) bit errors? > > ECC has single bit error correction and 2 bit error detection. Better than > parity no matter how you slice it. I have not tried it on D-P, but Rod says that the Triton-II ECC imposes an extra delay in memory accesses, i.e. "don't use it". That should be really easy to see if you go looking for it. ... Joe ------------------------------------------------------------------------------- Joe Greco - Systems Administrator jgreco@ns.sol.net Solaria Public Access UNIX - Milwaukee, WI 414/546-7968
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