From owner-freebsd-hardware Tue May 14 09:34:03 1996 Return-Path: owner-hardware Received: (from root@localhost) by freefall.freebsd.org (8.7.3/8.7.3) id JAA22089 for hardware-outgoing; Tue, 14 May 1996 09:34:03 -0700 (PDT) Received: from brasil.moneng.mei.com (brasil.moneng.mei.com [151.186.109.160]) by freefall.freebsd.org (8.7.3/8.7.3) with ESMTP id JAA22084; Tue, 14 May 1996 09:34:01 -0700 (PDT) Received: (from jgreco@localhost) by brasil.moneng.mei.com (8.7.Beta.1/8.7.Beta.1) id LAA06612; Tue, 14 May 1996 11:30:00 -0500 From: Joe Greco Message-Id: <199605141630.LAA06612@brasil.moneng.mei.com> Subject: Re: Triton chipset with 256k cache caches 32M only? To: davidg@root.com Date: Tue, 14 May 1996 11:29:59 -0500 (CDT) Cc: mmead@Glock.COM, joerg_wunsch@uriah.heep.sax.de, blh@nol.net, jgreco@brasil.moneng.mei.com, hackers@freebsd.org, hardware@freebsd.org In-Reply-To: <199605141522.IAA12962@Root.COM> from "David Greenman" at May 14, 96 08:22:48 am X-Mailer: ELM [version 2.4 PL24] Content-Type: text Sender: owner-hardware@freebsd.org X-Loop: FreeBSD.org Precedence: bulk > >> No, it uses the parity bits. Only 8 syndrome bits are needed > >> for 64bit words. > > > > Hmm. So does that mean the ECC is limited to single (odd > >number of) bit errors? > > ECC has single bit error correction and 2 bit error detection. Better than > parity no matter how you slice it. I have not tried it on D-P, but Rod says that the Triton-II ECC imposes an extra delay in memory accesses, i.e. "don't use it". That should be really easy to see if you go looking for it. ... Joe ------------------------------------------------------------------------------- Joe Greco - Systems Administrator jgreco@ns.sol.net Solaria Public Access UNIX - Milwaukee, WI 414/546-7968