Date: Mon, 29 Dec 2003 12:20:32 -0800 (PST) From: admin@forkthepenguin.com To: Damian Gerow <damian@sentex.net> Cc: freebsd-hardware@freebsd.org Subject: Re: Kernel Optimizations for Processors Message-ID: <Pine.BSI.4.58L.0312291113340.15944@vp4.netgate.net> In-Reply-To: <20031229190146.GR883@sentex.net> References: <Pine.BSI.4.58L.0312272056370.9032@vp4.netgate.net> <20031229190146.GR883@sentex.net>
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Damian, thanks for the reply. > There's been a number of discussions about this over the past few months. > Take a quick peak through the archives. I looked through the archives using the search on the FreeBSD site, and Google (summaries are nice to have) and I didn't see a whole lot on this. Perhaps I'm just using the wrong search terms or getting too many false positives. > In short: the GCC folk (at least for 2.95.x) assume that a 686-compatible > chip understands CMOV. *Some* of the C3 cores understand it, others do not. > I was under the impression that the Samuel2 /did/ understand it. > Understanding CMOV is not a requirement for 686. OK, that clears things up a bit. I see now that this is listed in the "Features" in dmesg on a PentiumIII system. I found the following on the via site that discusses CMOV and is also related to the CMPXCHG8B code )see NO_F00F_HACK below). http://www.viaarena.com/?PageID=377 > I think you get ever-so-slightly better performance if you set your ARCH to > k6-2, though I use mine as i586/mmx. As for the kernel configuration, I > left mine at I686_CPU, as the C3 /is/ a 686-class CPU. What kernel option do you use for k6-2? I don't see anything in LINT or GENERIC. Also, what do you mean by "I use mine as i586/mmx"? Is this another kernel option? > > # CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD > > # K5/K6/K6-2 cpus. > > Used it, never bothered to see if it made a difference. <snip> > > # CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs > > # without cache flush at hold state, and (2) write-back CPU cache on > > # Cyrix 6x86 whose revision < 2.7 (NOTE 2). > > Used it, never bothered to see if it made a difference. > > > # NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY > > # Pentiums) from locking up when a LOCK CMPXCHG8B instruction is > > # executed. This option is only needed if I586_CPU is also defined, > > # and should be included for any non-Pentium CPU that defines it. > > 'and ONLY Pentiums' It also says "should be included for any non-Pentium CPU that defines it" but how do you know if the C# defines this? Is this another item that would show up in the "Features" list? I looked at a PI-133 I have and don't see it : CPU: Pentium/P54C (133.16-MHz 586-class CPU) Origin = "GenuineIntel" Id = 0x52c Stepping = 12 Features=0x3bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,APIC> I have a PII-300 running Fedora, but dmesg doesn't show the features. I did find it in proc : grep flags /proc/cpuinfo flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov mmx But again, I don't see anything like CMPXCHG8B (which apparently stands for "Compare and Exchange Eight Bytes". I did fint a thread on the OpenBSD list the eludes that the VIA Cyrix III supports this : http://www.monkey.org/openbsd/archive/bugs/0103/msg00127.html This feature is also reported in the C3 datasheet, it seems this is reported in the CPUID (Features) as CX8. http://www.viavpsd.com/product/6/13/%20VIA_C3_EBGA%20datasheet110.pdf So it seems like it "should be included for any non-Pentium CPU that defines it", but it sounds like it may not be an issue if this feature is implemented correctly... BTW, do you have problems with your system hanging on a reboot? I reported this as a bug (misc/60646) which I see has been reported at least twice before but nothing in the knats database shows it as being solved. Do you know of a fix for this? Thanks again, Chris
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