From owner-p4-projects@FreeBSD.ORG Tue Sep 26 14:45:37 2006 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id D3F5916A417; Tue, 26 Sep 2006 14:45:36 +0000 (UTC) X-Original-To: perforce@FreeBSD.org Delivered-To: perforce@FreeBSD.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 943B916A412 for ; Tue, 26 Sep 2006 14:45:36 +0000 (UTC) (envelope-from attilio@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 4C48843D45 for ; Tue, 26 Sep 2006 14:45:36 +0000 (GMT) (envelope-from attilio@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.6/8.13.6) with ESMTP id k8QEjaec037215 for ; Tue, 26 Sep 2006 14:45:36 GMT (envelope-from attilio@FreeBSD.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.6/8.13.4/Submit) id k8QEjZC9037211 for perforce@freebsd.org; Tue, 26 Sep 2006 14:45:35 GMT (envelope-from attilio@FreeBSD.org) Date: Tue, 26 Sep 2006 14:45:35 GMT Message-Id: <200609261445.k8QEjZC9037211@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to attilio@FreeBSD.org using -f From: Attilio Rao To: Perforce Change Reviews Cc: Subject: PERFORCE change 106723 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Sep 2006 14:45:37 -0000 http://perforce.freebsd.org/chv.cgi?CH=106723 Change 106723 by attilio@attilio_laptop on 2006/09/26 14:45:23 Style-ize them Affected files ... .. //depot/projects/usb/src/sys/dev/usb/if_cdcereg.h#7 edit .. //depot/projects/usb/src/sys/dev/usb/if_cuereg.h#5 edit .. //depot/projects/usb/src/sys/dev/usb/if_kuereg.h#5 edit .. //depot/projects/usb/src/sys/dev/usb/if_ruereg.h#5 edit Differences ... ==== //depot/projects/usb/src/sys/dev/usb/if_cdcereg.h#7 (text+ko) ==== @@ -39,7 +39,7 @@ struct cdce_type { struct usb_devno cdce_dev; - u_int16_t cdce_flags; + uint16_t cdce_flags; }; struct cdce_softc { ==== //depot/projects/usb/src/sys/dev/usb/if_cuereg.h#5 (text+ko) ==== @@ -36,105 +36,88 @@ * Definitions for the CATC Netmate II USB to ethernet controller. */ - -/* - * Vendor specific control commands. - */ -#define CUE_CMD_RESET 0xF4 -#define CUE_CMD_GET_MACADDR 0xF2 -#define CUE_CMD_WRITEREG 0xFA -#define CUE_CMD_READREG 0xFB -#define CUE_CMD_READSRAM 0xF1 -#define CUE_CMD_WRITESRAM 0xFC - -/* - * Internal registers - */ -#define CUE_TX_BUFCNT 0x20 -#define CUE_RX_BUFCNT 0x21 -#define CUE_ADVANCED_OPMODES 0x22 -#define CUE_TX_BUFPKTS 0x23 -#define CUE_RX_BUFPKTS 0x24 -#define CUE_RX_MAXCHAIN 0x25 - -#define CUE_ETHCTL 0x60 -#define CUE_ETHSTS 0x61 -#define CUE_PAR5 0x62 -#define CUE_PAR4 0x63 -#define CUE_PAR3 0x64 -#define CUE_PAR2 0x65 -#define CUE_PAR1 0x66 -#define CUE_PAR0 0x67 - +/* Vendor specific control commands. */ +#define CUE_CMD_RESET 0xF4 +#define CUE_CMD_GET_MACADDR 0xF2 +#define CUE_CMD_WRITEREG 0xFA +#define CUE_CMD_READREG 0xFB +#define CUE_CMD_READSRAM 0xF1 +#define CUE_CMD_WRITESRAM 0xFC +/* Internal registers. */ +#define CUE_TX_BUFCNT 0x20 +#define CUE_RX_BUFCNT 0x21 +#define CUE_ADVANCED_OPMODES 0x22 +#define CUE_TX_BUFPKTS 0x23 +#define CUE_RX_BUFPKTS 0x24 +#define CUE_RX_MAXCHAIN 0x25 +#define CUE_ETHCTL 0x60 +#define CUE_ETHSTS 0x61 +#define CUE_PAR5 0x62 +#define CUE_PAR4 0x63 +#define CUE_PAR3 0x64 +#define CUE_PAR2 0x65 +#define CUE_PAR1 0x66 +#define CUE_PAR0 0x67 /* Error counters, all 16 bits wide. */ -#define CUE_TX_SINGLECOLL 0x69 -#define CUE_TX_MULTICOLL 0x6B -#define CUE_TX_EXCESSCOLL 0x6D -#define CUE_RX_FRAMEERR 0x6F +#define CUE_TX_SINGLECOLL 0x69 +#define CUE_TX_MULTICOLL 0x6B +#define CUE_TX_EXCESSCOLL 0x6D +#define CUE_RX_FRAMEERR 0x6F +#define CUE_LEDCTL 0x81 +/* Advenced operating mode register. */ +#define CUE_AOP_SRAMWAITS 0x03 +#define CUE_AOP_EMBED_RXLEN 0x08 +#define CUE_AOP_RXCOMBINE 0x10 +#define CUE_AOP_TXCOMBINE 0x20 +#define CUE_AOP_EVEN_PKT_READS 0x40 +#define CUE_AOP_LOOPBK 0x80 +/* Ethernet control register. */ +#define CUE_ETHCTL_RX_ON 0x01 +#define CUE_ETHCTL_LINK_POLARITY 0x02 +#define CUE_ETHCTL_LINK_FORCE_OK 0x04 +#define CUE_ETHCTL_MCAST_ON 0x08 +#define CUE_ETHCTL_PROMISC 0x10 +/* Ethernet status register. */ +#define CUE_ETHSTS_NO_CARRIER 0x01 +#define CUE_ETHSTS_LATECOLL 0x02 +#define CUE_ETHSTS_EXCESSCOLL 0x04 +#define CUE_ETHSTS_TXBUF_AVAIL 0x08 +#define CUE_ETHSTS_BAD_POLARITY 0x10 +#define CUE_ETHSTS_LINK_OK 0x20 +/* LED control register. */ +#define CUE_LEDCTL_BLINK_1X 0x00 +#define CUE_LEDCTL_BLINK_2X 0x01 +#define CUE_LEDCTL_BLINK_QUARTER_ON 0x02 +#define CUE_LEDCTL_BLINK_QUARTER_OFF 0x03 +#define CUE_LEDCTL_OFF 0x04 +#define CUE_LEDCTL_FOLLOW_LINK 0x08 -#define CUE_LEDCTL 0x81 - -/* Advenced operating mode register */ -#define CUE_AOP_SRAMWAITS 0x03 -#define CUE_AOP_EMBED_RXLEN 0x08 -#define CUE_AOP_RXCOMBINE 0x10 -#define CUE_AOP_TXCOMBINE 0x20 -#define CUE_AOP_EVEN_PKT_READS 0x40 -#define CUE_AOP_LOOPBK 0x80 - -/* Ethernet control register */ -#define CUE_ETHCTL_RX_ON 0x01 -#define CUE_ETHCTL_LINK_POLARITY 0x02 -#define CUE_ETHCTL_LINK_FORCE_OK 0x04 -#define CUE_ETHCTL_MCAST_ON 0x08 -#define CUE_ETHCTL_PROMISC 0x10 - -/* Ethernet status register */ -#define CUE_ETHSTS_NO_CARRIER 0x01 -#define CUE_ETHSTS_LATECOLL 0x02 -#define CUE_ETHSTS_EXCESSCOLL 0x04 -#define CUE_ETHSTS_TXBUF_AVAIL 0x08 -#define CUE_ETHSTS_BAD_POLARITY 0x10 -#define CUE_ETHSTS_LINK_OK 0x20 - -/* LED control register */ -#define CUE_LEDCTL_BLINK_1X 0x00 -#define CUE_LEDCTL_BLINK_2X 0x01 -#define CUE_LEDCTL_BLINK_QUARTER_ON 0x02 -#define CUE_LEDCTL_BLINK_QUARTER_OFF 0x03 -#define CUE_LEDCTL_OFF 0x04 -#define CUE_LEDCTL_FOLLOW_LINK 0x08 - /* - * Address in ASIC's internal SRAM where the - * multicast hash table lives. The table is 64 bytes long, - * giving us a 512-bit table. We have to set the bit that - * corresponds to the broadcast address in order to enable + * Address in ASIC's internal SRAM where the multicast hash table lives. + * The table is 64 bytes long, giving us a 512-bit table. We have to set + * the bit that corresponds to the broadcast address in order to enable * reception of broadcast frames. */ -#define CUE_MCAST_TABLE_ADDR 0xFA80 -#define CUE_MCAST_TABLE_LEN 64 +#define CUE_MCAST_TABLE_ADDR 0xFA80 +#define CUE_MCAST_TABLE_LEN 64 -#define CUE_TIMEOUT 1000 -#define CUE_MIN_FRAMELEN 60 -#define CUE_RX_FRAMES 1 -#define CUE_TX_FRAMES 1 +#define CUE_TIMEOUT 1000 +#define CUE_MIN_FRAMELEN 60 +#define CUE_RX_FRAMES 1 +#define CUE_TX_FRAMES 1 -#define CUE_CTL_READ 0x01 -#define CUE_CTL_WRITE 0x02 +#define CUE_CTL_READ 0x01 +#define CUE_CTL_WRITE 0x02 -#define CUE_CONFIG_NO 1 -#define CUE_IFACE_IDX 0 +#define CUE_CONFIG_NO 1 +#define CUE_IFACE_IDX 0 -/* - * The interrupt endpoint is currently unused - * by the KLSI part. - */ -#define CUE_ENDPT_MAX 4 +/* The interrupt endpoint is currently unused by the KLSI part. */ +#define CUE_ENDPT_MAX 4 struct cue_type { - u_int16_t cue_vid; - u_int16_t cue_did; + uint16_t cue_vid; + uint16_t cue_did; }; struct cue_softc { @@ -143,23 +126,23 @@ struct __callout sc_watchdog; struct mtx sc_mtx; - struct ifnet * sc_ifp; + struct ifnet *sc_ifp; device_t sc_dev; - struct usbd_device * sc_udev; - struct usbd_xfer * sc_xfer[CUE_ENDPT_MAX]; + struct usbd_device *sc_udev; + struct usbd_xfer *sc_xfer[CUE_ENDPT_MAX]; - u_int32_t sc_unit; + uint32_t sc_unit; - u_int16_t sc_flags; -#define CUE_FLAG_READ_STALL 0x0010 /* wait for clearing of stall */ -#define CUE_FLAG_WRITE_STALL 0x0020 /* wait for clearing of stall */ -#define CUE_FLAG_LL_READY 0x0040 /* Lower Layer Ready */ -#define CUE_FLAG_HL_READY 0x0080 /* Higher Layer Ready */ -#define CUE_FLAG_INTR_STALL 0x0100 /* wait for clearing of stall */ + uint16_t sc_flags; +#define CUE_FLAG_READ_STALL 0x0010 /* wait for clearing of stall */ +#define CUE_FLAG_WRITE_STALL 0x0020 /* wait for clearing of stall */ +#define CUE_FLAG_LL_READY 0x0040 /* Lower Layer Ready */ +#define CUE_FLAG_HL_READY 0x0080 /* Higher Layer Ready */ +#define CUE_FLAG_INTR_STALL 0x0100 /* wait for clearing of stall */ }; struct cue_config_copy { - u_int32_t if_flags; - u_int8_t if_lladdr[ETHER_ADDR_LEN]; - u_int8_t if_hash[CUE_MCAST_TABLE_LEN]; + uint32_t if_flags; + uint8_t if_lladdr[ETHER_ADDR_LEN]; + uint8_t if_hash[CUE_MCAST_TABLE_LEN]; }; ==== //depot/projects/usb/src/sys/dev/usb/if_kuereg.h#5 (text+ko) ==== @@ -36,102 +36,93 @@ * Definitions for the KLSI KL5KUSB101B USB to ethernet controller. * The KLSI part is controlled via vendor control requests, the structure * of which depend a bit on the firmware running on the internal - * microcontroller. The one exception is the 'send scan data' command, + * microcontroller. The one exception is the 'send scan data' command, * which is used to load the firmware. */ -#define KUE_CMD_GET_ETHER_DESCRIPTOR 0x00 -#define KUE_CMD_SET_MCAST_FILTERS 0x01 -#define KUE_CMD_SET_PKT_FILTER 0x02 -#define KUE_CMD_GET_ETHERSTATS 0x03 -#define KUE_CMD_GET_GPIO 0x04 -#define KUE_CMD_SET_GPIO 0x05 -#define KUE_CMD_SET_MAC 0x06 -#define KUE_CMD_GET_MAC 0x07 -#define KUE_CMD_SET_URB_SIZE 0x08 -#define KUE_CMD_SET_SOFS 0x09 -#define KUE_CMD_SET_EVEN_PKTS 0x0A -#define KUE_CMD_SEND_SCAN 0xFF +#define KUE_CMD_GET_ETHER_DESCRIPTOR 0x00 +#define KUE_CMD_SET_MCAST_FILTERS 0x01 +#define KUE_CMD_SET_PKT_FILTER 0x02 +#define KUE_CMD_GET_ETHERSTATS 0x03 +#define KUE_CMD_GET_GPIO 0x04 +#define KUE_CMD_SET_GPIO 0x05 +#define KUE_CMD_SET_MAC 0x06 +#define KUE_CMD_GET_MAC 0x07 +#define KUE_CMD_SET_URB_SIZE 0x08 +#define KUE_CMD_SET_SOFS 0x09 +#define KUE_CMD_SET_EVEN_PKTS 0x0A +#define KUE_CMD_SEND_SCAN 0xFF struct kue_ether_desc { - u_int8_t kue_len; - u_int8_t kue_rsvd0; - u_int8_t kue_rsvd1; - u_int8_t kue_macaddr[ETHER_ADDR_LEN]; - u_int8_t kue_etherstats[4]; - u_int8_t kue_maxseg[2]; - u_int8_t kue_mcastfilt[2]; - u_int8_t kue_rsvd2; -} UPACKED; + uint8_t kue_len; + uint8_t kue_rsvd0; + uint8_t kue_rsvd1; + uint8_t kue_macaddr[ETHER_ADDR_LEN]; + uint8_t kue_etherstats[4]; + uint8_t kue_maxseg[2]; + uint8_t kue_mcastfilt[2]; + uint8_t kue_rsvd2; +} __packed; -#define KUE_ETHERSTATS(x) \ - UGETDW((x)->sc_desc.kue_etherstats) +#define KUE_ETHERSTATS(x) UGETDW((x)->sc_desc.kue_etherstats) +#define KUE_MAXSEG(x) UGETW((x)->sc_desc.kue_maxseg) +#define KUE_MCFILTCNT(x) (UGETW((x)->sc_desc.kue_mcastfilt) & 0x7FFF) +#define KUE_MCFILT(x, y) \ + ((x)->sc_mcfilters + ((y) * ETHER_ADDR_LEN)) -#define KUE_MAXSEG(x) \ - UGETW((x)->sc_desc.kue_maxseg) +#define KUE_MCFILT_MAX 64 -#define KUE_MCFILTCNT(x) \ - (UGETW((x)->sc_desc.kue_mcastfilt) & 0x7FFF) +#define KUE_STAT_TX_OK 0x00000001 +#define KUE_STAT_RX_OK 0x00000002 +#define KUE_STAT_TX_ERR 0x00000004 +#define KUE_STAT_RX_ERR 0x00000008 +#define KUE_STAT_RX_NOBUF 0x00000010 +#define KUE_STAT_TX_UCAST_BYTES 0x00000020 +#define KUE_STAT_TX_UCAST_FRAMES 0x00000040 +#define KUE_STAT_TX_MCAST_BYTES 0x00000080 +#define KUE_STAT_TX_MCAST_FRAMES 0x00000100 +#define KUE_STAT_TX_BCAST_BYTES 0x00000200 +#define KUE_STAT_TX_BCAST_FRAMES 0x00000400 +#define KUE_STAT_RX_UCAST_BYTES 0x00000800 +#define KUE_STAT_RX_UCAST_FRAMES 0x00001000 +#define KUE_STAT_RX_MCAST_BYTES 0x00002000 +#define KUE_STAT_RX_MCAST_FRAMES 0x00004000 +#define KUE_STAT_RX_BCAST_BYTES 0x00008000 +#define KUE_STAT_RX_BCAST_FRAMES 0x00010000 +#define KUE_STAT_RX_CRCERR 0x00020000 +#define KUE_STAT_TX_QUEUE_LENGTH 0x00040000 +#define KUE_STAT_RX_ALIGNERR 0x00080000 +#define KUE_STAT_TX_SINGLECOLL 0x00100000 +#define KUE_STAT_TX_MULTICOLL 0x00200000 +#define KUE_STAT_TX_DEFERRED 0x00400000 +#define KUE_STAT_TX_MAXCOLLS 0x00800000 +#define KUE_STAT_RX_OVERRUN 0x01000000 +#define KUE_STAT_TX_UNDERRUN 0x02000000 +#define KUE_STAT_TX_SQE_ERR 0x04000000 +#define KUE_STAT_TX_CARRLOSS 0x08000000 +#define KUE_STAT_RX_LATECOLL 0x10000000 -#define KUE_MCFILT(x, y) \ - ((x)->sc_mcfilters + ((y) * ETHER_ADDR_LEN)) +#define KUE_RXFILT_PROMISC 0x0001 +#define KUE_RXFILT_ALLMULTI 0x0002 +#define KUE_RXFILT_UNICAST 0x0004 +#define KUE_RXFILT_BROADCAST 0x0008 +#define KUE_RXFILT_MULTICAST 0x0010 -#define KUE_MCFILT_MAX 64 +#define KUE_TIMEOUT 1000 +#define KUE_MIN_FRAMELEN 60 -#define KUE_STAT_TX_OK 0x00000001 -#define KUE_STAT_RX_OK 0x00000002 -#define KUE_STAT_TX_ERR 0x00000004 -#define KUE_STAT_RX_ERR 0x00000008 -#define KUE_STAT_RX_NOBUF 0x00000010 -#define KUE_STAT_TX_UCAST_BYTES 0x00000020 -#define KUE_STAT_TX_UCAST_FRAMES 0x00000040 -#define KUE_STAT_TX_MCAST_BYTES 0x00000080 -#define KUE_STAT_TX_MCAST_FRAMES 0x00000100 -#define KUE_STAT_TX_BCAST_BYTES 0x00000200 -#define KUE_STAT_TX_BCAST_FRAMES 0x00000400 -#define KUE_STAT_RX_UCAST_BYTES 0x00000800 -#define KUE_STAT_RX_UCAST_FRAMES 0x00001000 -#define KUE_STAT_RX_MCAST_BYTES 0x00002000 -#define KUE_STAT_RX_MCAST_FRAMES 0x00004000 -#define KUE_STAT_RX_BCAST_BYTES 0x00008000 -#define KUE_STAT_RX_BCAST_FRAMES 0x00010000 -#define KUE_STAT_RX_CRCERR 0x00020000 -#define KUE_STAT_TX_QUEUE_LENGTH 0x00040000 -#define KUE_STAT_RX_ALIGNERR 0x00080000 -#define KUE_STAT_TX_SINGLECOLL 0x00100000 -#define KUE_STAT_TX_MULTICOLL 0x00200000 -#define KUE_STAT_TX_DEFERRED 0x00400000 -#define KUE_STAT_TX_MAXCOLLS 0x00800000 -#define KUE_STAT_RX_OVERRUN 0x01000000 -#define KUE_STAT_TX_UNDERRUN 0x02000000 -#define KUE_STAT_TX_SQE_ERR 0x04000000 -#define KUE_STAT_TX_CARRLOSS 0x08000000 -#define KUE_STAT_RX_LATECOLL 0x10000000 +#define KUE_CTL_READ 0x01 +#define KUE_CTL_WRITE 0x02 -#define KUE_RXFILT_PROMISC 0x0001 -#define KUE_RXFILT_ALLMULTI 0x0002 -#define KUE_RXFILT_UNICAST 0x0004 -#define KUE_RXFILT_BROADCAST 0x0008 -#define KUE_RXFILT_MULTICAST 0x0010 +#define KUE_CONFIG_NO 1 +#define KUE_IFACE_IDX 0 -#define KUE_TIMEOUT 1000 -#define KUE_MIN_FRAMELEN 60 - -#define KUE_CTL_READ 0x01 -#define KUE_CTL_WRITE 0x02 - -#define KUE_CONFIG_NO 1 -#define KUE_IFACE_IDX 0 - -/* - * The interrupt endpoint is currently unused - * by the KLSI part. - */ -#define KUE_ENDPT_MAX 4 +/* The interrupt endpoint is currently unused by the KLSI part. */ +#define KUE_ENDPT_MAX 4 struct kue_type { - u_int16_t kue_vid; - u_int16_t kue_did; + uint16_t kue_vid; + uint16_t kue_did; }; struct kue_softc { @@ -142,26 +133,26 @@ struct mtx sc_mtx; struct kue_ether_desc sc_desc; - struct ifnet * sc_ifp; + struct ifnet *sc_ifp; device_t sc_dev; - struct usbd_device * sc_udev; - struct usbd_xfer * sc_xfer[KUE_ENDPT_MAX]; + struct usbd_device *sc_udev; + struct usbd_xfer *sc_xfer[KUE_ENDPT_MAX]; - u_int32_t sc_unit; + uint32_t sc_unit; - u_int16_t sc_mcfilt_max; - u_int16_t sc_flags; -#define KUE_FLAG_READ_STALL 0x0010 /* wait for clearing of stall */ -#define KUE_FLAG_WRITE_STALL 0x0020 /* wait for clearing of stall */ -#define KUE_FLAG_LL_READY 0x0040 /* Lower Layer Ready */ -#define KUE_FLAG_HL_READY 0x0080 /* Higher Layer Ready */ -#define KUE_FLAG_INTR_STALL 0x0100 /* wait for clearing of stall */ + uint16_t sc_mcfilt_max; + uint16_t sc_flags; +#define KUE_FLAG_READ_STALL 0x0010 /* wait for clearing of stall */ +#define KUE_FLAG_WRITE_STALL 0x0020 /* wait for clearing of stall */ +#define KUE_FLAG_LL_READY 0x0040 /* Lower Layer Ready */ +#define KUE_FLAG_HL_READY 0x0080 /* Higher Layer Ready */ +#define KUE_FLAG_INTR_STALL 0x0100 /* wait for clearing of stall */ }; struct kue_config_copy { - u_int32_t if_flags; - u_int16_t if_rxfilt; - u_int16_t if_nhash; - u_int8_t if_lladdr[ETHER_ADDR_LEN]; - u_int8_t if_hash[KUE_MCFILT_MAX * ETHER_ADDR_LEN]; + uint32_t if_flags; + uint16_t if_rxfilt; + uint16_t if_nhash; + uint8_t if_lladdr[ETHER_ADDR_LEN]; + uint8_t if_hash[KUE_MCFILT_MAX * ETHER_ADDR_LEN]; }; ==== //depot/projects/usb/src/sys/dev/usb/if_ruereg.h#5 (text+ko) ==== @@ -26,152 +26,148 @@ * $FreeBSD: src/sys/dev/usb/if_ruereg.h,v 1.6 2005/06/10 16:49:15 brooks Exp $ */ -#define RUE_CONFIG_NO 1 -#define RUE_IFACE_IDX 0 +#ifndef _IF_RUEREG_H_ +#define _IF_RUEREG_H_ -#define RUE_ENDPT_MAX 6 +#define RUE_CONFIG_NO 1 +#define RUE_IFACE_IDX 0 -#define RUE_INTR_PKTLEN 0x8 +#define RUE_ENDPT_MAX 6 -#define RUE_TIMEOUT 50 -#define RUE_MIN_FRAMELEN 60 +#define RUE_INTR_PKTLEN 0x8 -/* - * Registers - */ +#define RUE_TIMEOUT 50 +#define RUE_MIN_FRAMELEN 60 -#define RUE_IDR0 0x0120 -#define RUE_IDR1 0x0121 -#define RUE_IDR2 0x0122 -#define RUE_IDR3 0x0123 -#define RUE_IDR4 0x0124 -#define RUE_IDR5 0x0125 +/* Registers. */ +#define RUE_IDR0 0x0120 +#define RUE_IDR1 0x0121 +#define RUE_IDR2 0x0122 +#define RUE_IDR3 0x0123 +#define RUE_IDR4 0x0124 +#define RUE_IDR5 0x0125 -#define RUE_MAR0 0x0126 -#define RUE_MAR1 0x0127 -#define RUE_MAR2 0x0128 -#define RUE_MAR3 0x0129 -#define RUE_MAR4 0x012A -#define RUE_MAR5 0x012B -#define RUE_MAR6 0x012C -#define RUE_MAR7 0x012D +#define RUE_MAR0 0x0126 +#define RUE_MAR1 0x0127 +#define RUE_MAR2 0x0128 +#define RUE_MAR3 0x0129 +#define RUE_MAR4 0x012A +#define RUE_MAR5 0x012B +#define RUE_MAR6 0x012C +#define RUE_MAR7 0x012D -#define RUE_CR 0x012E /* B, R/W */ -#define RUE_CR_SOFT_RST 0x10 -#define RUE_CR_RE 0x08 -#define RUE_CR_TE 0x04 -#define RUE_CR_EP3CLREN 0x02 +#define RUE_CR 0x012E /* B, R/W */ +#define RUE_CR_SOFT_RST 0x10 +#define RUE_CR_RE 0x08 +#define RUE_CR_TE 0x04 +#define RUE_CR_EP3CLREN 0x02 -#define RUE_TCR 0x012F /* B, R/W */ -#define RUE_TCR_TXRR1 0x80 -#define RUE_TCR_TXRR0 0x40 -#define RUE_TCR_IFG1 0x10 -#define RUE_TCR_IFG0 0x08 -#define RUE_TCR_NOCRC 0x01 -#define RUE_TCR_CONFIG (RUE_TCR_TXRR1|RUE_TCR_TXRR0|RUE_TCR_IFG1|RUE_TCR_IFG0) +#define RUE_TCR 0x012F /* B, R/W */ +#define RUE_TCR_TXRR1 0x80 +#define RUE_TCR_TXRR0 0x40 +#define RUE_TCR_IFG1 0x10 +#define RUE_TCR_IFG0 0x08 +#define RUE_TCR_NOCRC 0x01 +#define RUE_TCR_CONFIG (RUE_TCR_TXRR1 | RUE_TCR_TXRR0 | \ + RUE_TCR_IFG1 | RUE_TCR_IFG0) -#define RUE_RCR 0x0130 /* W, R/W */ -#define RUE_RCR_TAIL 0x80 -#define RUE_RCR_AER 0x40 -#define RUE_RCR_AR 0x20 -#define RUE_RCR_AM 0x10 -#define RUE_RCR_AB 0x08 -#define RUE_RCR_AD 0x04 -#define RUE_RCR_AAM 0x02 -#define RUE_RCR_AAP 0x01 -#define RUE_RCR_CONFIG (RUE_RCR_TAIL|RUE_RCR_AD) +#define RUE_RCR 0x0130 /* W, R/W */ +#define RUE_RCR_TAIL 0x80 +#define RUE_RCR_AER 0x40 +#define RUE_RCR_AR 0x20 +#define RUE_RCR_AM 0x10 +#define RUE_RCR_AB 0x08 +#define RUE_RCR_AD 0x04 +#define RUE_RCR_AAM 0x02 +#define RUE_RCR_AAP 0x01 +#define RUE_RCR_CONFIG (RUE_RCR_TAIL | RUE_RCR_AD) -#define RUE_TSR 0x0132 -#define RUE_RSR 0x0133 -#define RUE_CON0 0x0135 -#define RUE_CON1 0x0136 -#define RUE_MSR 0x0137 -#define RUE_PHYADD 0x0138 -#define RUE_PHYDAT 0x0139 +#define RUE_TSR 0x0132 +#define RUE_RSR 0x0133 +#define RUE_CON0 0x0135 +#define RUE_CON1 0x0136 +#define RUE_MSR 0x0137 +#define RUE_PHYADD 0x0138 +#define RUE_PHYDAT 0x0139 -#define RUE_PHYCNT 0x013B /* B, R/W */ -#define RUE_PHYCNT_PHYOWN 0x40 -#define RUE_PHYCNT_RWCR 0x20 +#define RUE_PHYCNT 0x013B /* B, R/W */ +#define RUE_PHYCNT_PHYOWN 0x40 +#define RUE_PHYCNT_RWCR 0x20 -#define RUE_GPPC 0x013D -#define RUE_WAKECNT 0x013E +#define RUE_GPPC 0x013D +#define RUE_WAKECNT 0x013E -#define RUE_BMCR 0x0140 -#define RUE_BMCR_SPD_SET 0x2000 -#define RUE_BMCR_DUPLEX 0x0100 +#define RUE_BMCR 0x0140 +#define RUE_BMCR_SPD_SET 0x2000 +#define RUE_BMCR_DUPLEX 0x0100 -#define RUE_BMSR 0x0142 +#define RUE_BMSR 0x0142 -#define RUE_ANAR 0x0144 /* W, R/W */ -#define RUE_ANAR_PAUSE 0x0400 +#define RUE_ANAR 0x0144 /* W, R/W */ +#define RUE_ANAR_PAUSE 0x0400 -#define RUE_ANLP 0x0146 /* W, R/O */ -#define RUE_ANLP_PAUSE 0x0400 +#define RUE_ANLP 0x0146 /* W, R/O */ +#define RUE_ANLP_PAUSE 0x0400 -#define RUE_AER 0x0148 +#define RUE_AER 0x0148 -#define RUE_NWAYT 0x014A -#define RUE_CSCR 0x014C +#define RUE_NWAYT 0x014A +#define RUE_CSCR 0x014C -#define RUE_CRC0 0x014E -#define RUE_CRC1 0x0150 -#define RUE_CRC2 0x0152 -#define RUE_CRC3 0x0154 -#define RUE_CRC4 0x0156 +#define RUE_CRC0 0x014E +#define RUE_CRC1 0x0150 +#define RUE_CRC2 0x0152 +#define RUE_CRC3 0x0154 +#define RUE_CRC4 0x0156 -#define RUE_BYTEMASK0 0x0158 -#define RUE_BYTEMASK1 0x0160 -#define RUE_BYTEMASK2 0x0168 -#define RUE_BYTEMASK3 0x0170 -#define RUE_BYTEMASK4 0x0178 +#define RUE_BYTEMASK0 0x0158 +#define RUE_BYTEMASK1 0x0160 +#define RUE_BYTEMASK2 0x0168 +#define RUE_BYTEMASK3 0x0170 +#define RUE_BYTEMASK4 0x0178 -#define RUE_PHY1 0x0180 -#define RUE_PHY2 0x0184 +#define RUE_PHY1 0x0180 +#define RUE_PHY2 0x0184 -#define RUE_TW1 0x0186 +#define RUE_TW1 0x0186 -#define RUE_REG_MIN 0x0120 -#define RUE_REG_MAX 0x0189 +#define RUE_REG_MIN 0x0120 +#define RUE_REG_MAX 0x0189 -/* - * EEPROM address declarations - */ +/* EEPROM address declarations. */ +#define RUE_EEPROM_BASE 0x1200 +#define RUE_EEPROM_IDR0 (RUE_EEPROM_BASE + 0x02) +#define RUE_EEPROM_IDR1 (RUE_EEPROM_BASE + 0x03) +#define RUE_EEPROM_IDR2 (RUE_EEPROM_BASE + 0x03) +#define RUE_EEPROM_IDR3 (RUE_EEPROM_BASE + 0x03) +#define RUE_EEPROM_IDR4 (RUE_EEPROM_BASE + 0x03) +#define RUE_EEPROM_IDR5 (RUE_EEPROM_BASE + 0x03) +#define RUE_EEPROM_INTERVAL (RUE_EEPROM_BASE + 0x17) -#define RUE_EEPROM_BASE 0x1200 +#define RUE_RXSTAT_VALID (0x01 << 12) +#define RUE_RXSTAT_RUNT (0x02 << 12) +#define RUE_RXSTAT_PMATCH (0x04 << 12) +#define RUE_RXSTAT_MCAST (0x08 << 12) -#define RUE_EEPROM_IDR0 (RUE_EEPROM_BASE + 0x02) -#define RUE_EEPROM_IDR1 (RUE_EEPROM_BASE + 0x03) -#define RUE_EEPROM_IDR2 (RUE_EEPROM_BASE + 0x03) -#define RUE_EEPROM_IDR3 (RUE_EEPROM_BASE + 0x03) -#define RUE_EEPROM_IDR4 (RUE_EEPROM_BASE + 0x03) -#define RUE_EEPROM_IDR5 (RUE_EEPROM_BASE + 0x03) - -#define RUE_EEPROM_INTERVAL (RUE_EEPROM_BASE + 0x17) +#define GET_MII(sc) ((sc)->sc_miibus ? \ + device_get_softc((sc)->sc_miibus) : NULL) struct rue_intrpkt { - u_int8_t rue_tsr; - u_int8_t rue_rsr; - u_int8_t rue_gep_msr; - u_int8_t rue_waksr; - u_int8_t rue_txok_cnt; - u_int8_t rue_rxlost_cnt; - u_int8_t rue_crcerr_cnt; - u_int8_t rue_col_cnt; -} UPACKED; + uint8_t rue_tsr; + uint8_t rue_rsr; + uint8_t rue_gep_msr; + uint8_t rue_waksr; + uint8_t rue_txok_cnt; + uint8_t rue_rxlost_cnt; + uint8_t rue_crcerr_cnt; + uint8_t rue_col_cnt; +} __packed; -#define RUE_RXSTAT_VALID (0x01 << 12) -#define RUE_RXSTAT_RUNT (0x02 << 12) -#define RUE_RXSTAT_PMATCH (0x04 << 12) -#define RUE_RXSTAT_MCAST (0x08 << 12) - struct rue_type { - u_int16_t rue_vid; - u_int16_t rue_did; + uint16_t rue_vid; + uint16_t rue_did; }; -#define GET_MII(sc) ((sc)->sc_miibus ? \ - device_get_softc((sc)->sc_miibus) : NULL) - struct rue_softc { struct usbd_config_td sc_config_td; @@ -179,29 +175,31 @@ struct __callout sc_watchdog; struct mtx sc_mtx; - struct ifnet * sc_ifp; - struct usbd_device * sc_udev; - struct usbd_xfer * sc_xfer[RUE_ENDPT_MAX]; + struct ifnet *sc_ifp; + struct usbd_device *sc_udev; + struct usbd_xfer *sc_xfer[RUE_ENDPT_MAX]; device_t sc_miibus; device_t sc_dev; - u_int32_t sc_unit; - u_int32_t sc_media_active; - u_int32_t sc_media_status; + uint32_t sc_unit; + uint32_t sc_media_active; + uint32_t sc_media_status; - u_int16_t sc_flags; -#define RUE_FLAG_WAIT_LINK 0x0001 -#define RUE_FLAG_INTR_STALL 0x0002 -#define RUE_FLAG_READ_STALL 0x0004 -#define RUE_FLAG_WRITE_STALL 0x0008 -#define RUE_FLAG_LL_READY 0x0010 -#define RUE_FLAG_HL_READY 0x0020 + uint16_t sc_flags; +#define RUE_FLAG_WAIT_LINK 0x0001 +#define RUE_FLAG_INTR_STALL 0x0002 +#define RUE_FLAG_READ_STALL 0x0004 +#define RUE_FLAG_WRITE_STALL 0x0008 +#define RUE_FLAG_LL_READY 0x0010 +#define RUE_FLAG_HL_READY 0x0020 - u_int8_t sc_name[16]; + uint8_t sc_name[16]; }; struct rue_config_copy { - u_int32_t if_flags; - u_int32_t if_hashes[2]; - u_int8_t if_lladdr[ETHER_ADDR_LEN]; + uint32_t if_flags; + uint32_t if_hashes[2]; + uint8_t if_lladdr[ETHER_ADDR_LEN]; }; + +#endif /* _IF_RUEREG_H_ */