Date: Tue, 25 Oct 2016 16:25:06 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r307925 - in head/sys/arm: arm include Message-ID: <201610251625.u9PGP6Ji056694@repo.freebsd.org>
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Author: andrew Date: Tue Oct 25 16:25:06 2016 New Revision: 307925 URL: https://svnweb.freebsd.org/changeset/base/307925 Log: Remove arm11x6_setttb and armv7_setttb as they are unused. While here remove unneeded code from the ARMv7 cpu assembly code. Sponsored by: ABT Systems Ltd Modified: head/sys/arm/arm/cpufunc_asm_arm11x6.S head/sys/arm/arm/cpufunc_asm_armv7.S head/sys/arm/include/cpufunc.h Modified: head/sys/arm/arm/cpufunc_asm_arm11x6.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_arm11x6.S Tue Oct 25 16:22:43 2016 (r307924) +++ head/sys/arm/arm/cpufunc_asm_arm11x6.S Tue Oct 25 16:25:06 2016 (r307925) @@ -64,14 +64,6 @@ __FBSDID("$FreeBSD$"); .cpu arm1176jz-s -ENTRY(arm11x6_setttb) - mov r1, #0 - mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ - mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */ - mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */ - RET -END(arm11x6_setttb) - /* * Preload the cache before issuing the WFI by conditionally disabling the * mcr intstructions the first time around the loop. Ensure the function is Modified: head/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_armv7.S Tue Oct 25 16:22:43 2016 (r307924) +++ head/sys/arm/arm/cpufunc_asm_armv7.S Tue Oct 25 16:25:06 2016 (r307925) @@ -37,56 +37,16 @@ __FBSDID("$FreeBSD$"); .cpu cortex-a8 +#ifdef ELF_TRAMPOLINE .Lcoherency_level: .word _C_LABEL(arm_cache_loc) .Lcache_type: .word _C_LABEL(arm_cache_type) -.Larmv7_dcache_line_size: - .word _C_LABEL(arm_dcache_min_line_size) -.Larmv7_icache_line_size: - .word _C_LABEL(arm_icache_min_line_size) -.Larmv7_idcache_line_size: - .word _C_LABEL(arm_idcache_min_line_size) .Lway_mask: .word 0x3ff .Lmax_index: .word 0x7fff -.Lpage_mask: - .word 0xfff - -#define PT_NOS (1 << 5) -#define PT_S (1 << 1) -#define PT_INNER_NC 0 -#define PT_INNER_WT (1 << 0) -#define PT_INNER_WB ((1 << 0) | (1 << 6)) -#define PT_INNER_WBWA (1 << 6) -#define PT_OUTER_NC 0 -#define PT_OUTER_WT (2 << 3) -#define PT_OUTER_WB (3 << 3) -#define PT_OUTER_WBWA (1 << 3) -#ifdef SMP -#define PT_ATTR (PT_S|PT_INNER_WBWA|PT_OUTER_WBWA|PT_NOS) -#else -#define PT_ATTR (PT_INNER_WBWA|PT_OUTER_WBWA) -#endif - -ENTRY(armv7_setttb) - dsb - orr r0, r0, #PT_ATTR - mcr CP15_TTBR0(r0) - isb -#ifdef SMP - mcr CP15_TLBIALLIS -#else - mcr CP15_TLBIALL -#endif - dsb - isb - RET -END(armv7_setttb) - -#ifdef ELF_TRAMPOLINE /* Based on algorithm from ARM Architecture Reference Manual */ ENTRY(armv7_dcache_wbinv_all) stmdb sp!, {r4, r5, r6, r7, r8, r9} Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Tue Oct 25 16:22:43 2016 (r307924) +++ head/sys/arm/include/cpufunc.h Tue Oct 25 16:25:06 2016 (r307925) @@ -279,7 +279,6 @@ void armv6_idcache_wbinv_all (void); #endif #if defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || \ defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) -void armv7_setttb (u_int); void armv7_idcache_wbinv_all (void); void armv7_cpu_sleep (int); void armv7_setup (void); @@ -297,7 +296,6 @@ void pj4bv7_setup (void); #if defined(CPU_ARM1176) void arm11_drain_writebuf (void); -void arm11x6_setttb (u_int); void arm11x6_setup (void); void arm11x6_sleep (int); /* no ref. for errata */ #endif
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