From owner-svn-src-head@freebsd.org Tue Nov 29 13:03:44 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id DD5F4C5AADF; Tue, 29 Nov 2016 13:03:44 +0000 (UTC) (envelope-from kadesai@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B811F1BEC; Tue, 29 Nov 2016 13:03:44 +0000 (UTC) (envelope-from kadesai@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uATD3hIF057783; Tue, 29 Nov 2016 13:03:43 GMT (envelope-from kadesai@FreeBSD.org) Received: (from kadesai@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uATD3hUh057780; Tue, 29 Nov 2016 13:03:43 GMT (envelope-from kadesai@FreeBSD.org) Message-Id: <201611291303.uATD3hUh057780@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: kadesai set sender to kadesai@FreeBSD.org using -f From: Kashyap D Desai Date: Tue, 29 Nov 2016 13:03:43 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r309292 - head/sys/dev/mrsas X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Nov 2016 13:03:45 -0000 Author: kadesai Date: Tue Nov 29 13:03:43 2016 New Revision: 309292 URL: https://svnweb.freebsd.org/changeset/base/309292 Log: This patch will unblock SYNCHRONIZE_CACHE command to firmware, i.e. don't block the SYNCHRONIZE_CACHE command at driver instead of passing it to firmware for all Gen3 controllers. For Thunderbolt controller, keep the legacy behavior i.e. return the SYNCHRONIZE_CACHE command with success status from driver itself. There is Sysctl parameter 'block_sync_cache' is provided to enable customers either to block/unblock these commands to facilitate legacy behavior if there is a compatibility issue. Default value for module parameter is to unblock this command. Submitted by: Sumit Saxena Reviewed by: Kashyap Desai MFC after: 3 days Sponsored by: Broadcom Limited/AVAGO Technologies Modified: head/sys/dev/mrsas/mrsas.c head/sys/dev/mrsas/mrsas.h head/sys/dev/mrsas/mrsas_cam.c Modified: head/sys/dev/mrsas/mrsas.c ============================================================================== --- head/sys/dev/mrsas/mrsas.c Tue Nov 29 13:02:48 2016 (r309291) +++ head/sys/dev/mrsas/mrsas.c Tue Nov 29 13:03:43 2016 (r309292) @@ -432,6 +432,11 @@ mrsas_setup_sysctl(struct mrsas_softc *s OID_AUTO, "reset_in_progress", CTLFLAG_RD, &sc->reset_in_progress, 0, "ocr in progress status"); + SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), + OID_AUTO, "block_sync_cache", CTLFLAG_RW, + &sc->block_sync_cache, 0, + "Block SYNC CACHE at driver. "); + } /* @@ -451,6 +456,7 @@ mrsas_get_tunables(struct mrsas_softc *s sc->mrsas_fw_fault_check_delay = 1; sc->reset_count = 0; sc->reset_in_progress = 0; + sc->block_sync_cache = 0; /* * Grab the global variables. @@ -2438,12 +2444,21 @@ mrsas_ioc_init(struct mrsas_softc *sc) u_int8_t max_wait = MRSAS_IOC_INIT_WAIT_TIME; bus_addr_t phys_addr; int i, retcode = 0; + u_int32_t scratch_pad_2; /* Allocate memory for the IOC INIT command */ if (mrsas_alloc_ioc_cmd(sc)) { device_printf(sc->mrsas_dev, "Cannot allocate IOC command.\n"); return (1); } + + if (!sc->block_sync_cache) { + scratch_pad_2 = mrsas_read_reg(sc, offsetof(mrsas_reg_set, + outbound_scratch_pad_2)); + sc->fw_sync_cache_support = (scratch_pad_2 & + MR_CAN_HANDLE_SYNC_CACHE_OFFSET) ? 1 : 0; + } + IOCInitMsg = (pMpi2IOCInitRequest_t)(((char *)sc->ioc_init_mem) + 1024); IOCInitMsg->Function = MPI2_FUNCTION_IOC_INIT; IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER; Modified: head/sys/dev/mrsas/mrsas.h ============================================================================== --- head/sys/dev/mrsas/mrsas.h Tue Nov 29 13:02:48 2016 (r309291) +++ head/sys/dev/mrsas/mrsas.h Tue Nov 29 13:03:43 2016 (r309292) @@ -1334,7 +1334,6 @@ enum MR_EVT_ARGS { MR_EVT_ARGS_GENERIC, }; - /* * Thunderbolt (and later) Defines */ @@ -2085,6 +2084,11 @@ struct mrsas_ctrl_info { #define MR_MAX_MSIX_REG_ARRAY 16 /* + * SYNC CACHE offset define + */ +#define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 + +/* * FW reports the maximum of number of commands that it can accept (maximum * commands that can be outstanding) at any time. The driver must report a * lower number to the mid layer because it can issue a few internal commands @@ -2840,6 +2844,8 @@ struct mrsas_softc { u_int8_t do_timedout_reset; u_int32_t reset_in_progress; u_int32_t reset_count; + u_int32_t block_sync_cache; + u_int8_t fw_sync_cache_support; mrsas_atomic_t target_reset_outstanding; #define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS) struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS]; Modified: head/sys/dev/mrsas/mrsas_cam.c ============================================================================== --- head/sys/dev/mrsas/mrsas_cam.c Tue Nov 29 13:02:48 2016 (r309291) +++ head/sys/dev/mrsas/mrsas_cam.c Tue Nov 29 13:03:43 2016 (r309292) @@ -459,7 +459,8 @@ mrsas_startio(struct mrsas_softc *sc, st MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; u_int8_t cmd_type; - if ((csio->cdb_io.cdb_bytes[0]) == SYNCHRONIZE_CACHE) { + if ((csio->cdb_io.cdb_bytes[0]) == SYNCHRONIZE_CACHE && + (!sc->fw_sync_cache_support)) { ccb->ccb_h.status = CAM_REQ_CMP; xpt_done(ccb); return (0);